44 lines
880 B
Systemverilog
44 lines
880 B
Systemverilog
`timescale 1ns / 1ps
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module spd_reader_tb;
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reg clk, rst_n;
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wire scl, sda;
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// spd_reader DUT (
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// .i_clk(clk),
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// .i_rst_n(rst_n),
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// .i2c_scl(scl),
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// .i2c_sda(sda)
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// );
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spd_reader_top DUT (
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// clock and reset
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.sys_clk_p(clk),
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.sys_clk_n(!clk),
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.i_rst_n(rst_n),
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// i2c interface
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.i2c_scl(scl),
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.i2c_sda(sda),
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.i2c_lsb(),
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// fan
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.fan_pwm()
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);
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initial begin
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clk = 0;
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rst_n = 0;
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#100;
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rst_n = 1;
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wait(DUT.spd_reader_inst.find_i2c_address_done);
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#10_000;
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$stop;
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end
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always #2.5 clk = !clk; // 200MHz
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pullup pullup_scl(scl); // pullup scl line
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pullup pullup_sda(sda); // pullup sda line
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i2c_slave i2c_slave(
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.scl(scl),
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.sda(sda)
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);
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endmodule |