Angelo Jacobo 02d512df55 Delete sdram.txt		2023-05-28 16:20:52 +08:00
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DDR3 SDRAM Verilog Model	readme file from Micron	2023-05-28 16:14:21 +08:00
ddr3_controller.v	include only the controller (phy is now a separate module)	2023-05-28 16:18:14 +08:00
ddr3_phy.v	added phy interface (separated from controller)	2023-05-28 16:19:47 +08:00
ddr3_top.v	added top module which instantiates the controller and phy	2023-05-28 16:20:22 +08:00