UberDDR3/rtl
AngeloJacobo 4be9a30ff8 added files needed for icarus simulation (not yet working) 2025-05-18 15:24:10 +08:00
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axi update UberDDR3 AXI for Vivado custom IP 2025-02-16 14:53:05 +08:00
ecc Revert "add self-refresh option, passing Simulation, ongoing formal" 2024-11-23 11:43:05 +08:00
ecp5_phy added support for DLL_OFF and Lattice ECP5 PHY 2025-04-19 13:24:20 +08:00
spd added simulation and project demo with XADC 2025-01-12 14:55:43 +08:00
ddr3_controller.v fixed late_dq logic 2025-05-12 18:27:57 +08:00
ddr3_phy.v added files needed for icarus simulation (not yet working) 2025-05-18 15:24:10 +08:00
ddr3_top.v set default BIST_MODE to 1 for shorter bring up 2025-04-19 13:37:58 +08:00