314 lines
17 KiB
Verilog
314 lines
17 KiB
Verilog
`default_nettype none
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`timescale 1ps / 1ps
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module ddr3_top #(
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parameter CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
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DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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ROW_BITS = 14, //width of row address
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COL_BITS = 10, //width of column address
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BA_BITS = 3, //width of bank address
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DQ_BITS = 8, //device width
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LANES = 8, //number of DDR3 device to be controlled
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AUX_WIDTH = 4, //width of aux line (must be >= 4)
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WB2_ADDR_BITS = 7, //width of 2nd wishbone address bus
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WB2_DATA_BITS = 32, //width of 2nd wishbone data bus
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/* verilator lint_off UNUSEDPARAM */
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parameter[0:0] OPT_LOWPOWER = 1, //1 = low power, 0 = low logic
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OPT_BUS_ABORT = 1, //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
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/* verilator lint_on UNUSEDPARAM */
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MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
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SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone is needed
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parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
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serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
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wb_addr_bits = ROW_BITS + COL_BITS + BA_BITS - $clog2(serdes_ratio*2),
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wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
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wb_sel_bits = wb_data_bits / 8,
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wb2_sel_bits = WB2_DATA_BITS / 8,
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//4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
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cmd_len = 4 + 3 + BA_BITS + ROW_BITS
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)
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(
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input wire i_controller_clk, i_ddr3_clk, i_ref_clk, //i_controller_clk = CONTROLLER_CLK_PERIOD, i_ddr3_clk = DDR3_CLK_PERIOD, i_ref_clk = 200MHz
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input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
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input wire i_rst_n,
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//
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// Wishbone inputs
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input wire i_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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input wire i_wb_stb, //request a transfer
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input wire i_wb_we, //write-enable (1 = write, 0 = read)
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input wire[wb_addr_bits - 1:0] i_wb_addr, //burst-addressable {row,bank,col}
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input wire[wb_data_bits - 1:0] i_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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input wire[wb_sel_bits - 1:0] i_wb_sel, //byte strobe for write (1 = write the byte)
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input wire[AUX_WIDTH - 1:0] i_aux, //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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output wire o_wb_stall, //1 = busy, cannot accept requests
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output wire o_wb_ack, //1 = read/write request has completed
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output wire[wb_data_bits - 1:0] o_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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output wire[AUX_WIDTH - 1:0] o_aux, //for AXI-interface compatibility (given upon strobe)
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//
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// Wishbone 2 (PHY) inputs
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input wire i_wb2_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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input wire i_wb2_stb, //request a transfer
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input wire i_wb2_we, //write-enable (1 = write, 0 = read)
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input wire[WB2_ADDR_BITS - 1:0] i_wb2_addr, // memory-mapped register to be accessed
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input wire[WB2_DATA_BITS - 1:0] i_wb2_data, //write data
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input wire[wb2_sel_bits - 1:0] i_wb2_sel, //byte strobe for write (1 = write the byte)
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// Wishbone 2 (Controller) outputs
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output wire o_wb2_stall, //1 = busy, cannot accept requests
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output wire o_wb2_ack, //1 = read/write request has completed
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output wire[WB2_DATA_BITS - 1:0] o_wb2_data, //read data
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//
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// DDR3 I/O Interface
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output wire o_ddr3_clk_p, o_ddr3_clk_n,
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output wire o_ddr3_reset_n,
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output wire o_ddr3_cke, // CKE
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output wire o_ddr3_cs_n, // chip select signal
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output wire o_ddr3_ras_n, // RAS#
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output wire o_ddr3_cas_n, // CAS#
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output wire o_ddr3_we_n, // WE#
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output wire[ROW_BITS-1:0] o_ddr3_addr,
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output wire[BA_BITS-1:0] o_ddr3_ba_addr,
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inout wire[(DQ_BITS*LANES)-1:0] io_ddr3_dq,
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inout wire[(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
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output wire[LANES-1:0] o_ddr3_dm,
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output wire o_ddr3_odt, // on-die termination
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//
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// Debug outputs
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output wire[31:0] o_debug1,
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output wire[31:0] o_debug2,
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output wire[31:0] o_debug3,
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output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
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output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_n
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);
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// Instantiation Template
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/*
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// DDR3 Controller
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ddr3_top #(
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.CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.ROW_BITS(14), //width of row address
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.COL_BITS(10), //width of column address
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.BA_BITS(3), //width of bank address
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.DQ_BITS(8), //device width
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.LANES(2), //number of DDR3 device to be controlled
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.AUX_WIDTH(4), //width of aux line (must be >= 4)
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.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
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.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
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.OPT_LOWPOWER(1), //1 = low power, 0 = low logic
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.OPT_BUS_ABORT(1), //1 = can abort bus, 0 = no absort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
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.MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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.ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
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.SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed
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) ddr3_top
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(
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//clock and reset
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.i_controller_clk(i_controller_clk),
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.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
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.i_ref_clk(i_ref_clk),
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.i_ddr3_clk_90(i_ddr3_clk_90),
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.i_rst_n(!i_rst && clk_locked),
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//
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// Wishbone inputs
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.i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(i_wb_stb), //request a transfer
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.i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col}
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.i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
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.i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
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.o_wb_ack(o_wb_ack), //1 = read/write request has completed
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.o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_aux(o_aux),
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//
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// Wishbone 2 (PHY) inputs
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.i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb2_stb(), //request a transfer
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.i_wb2_we(), //write-enable (1 = write, 0 = read)
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.i_wb2_addr(), //burst-addressable {row,bank,col}
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.i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb2_sel(), //byte strobe for write (1 = write the byte)
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// Wishbone 2 (Controller) outputs
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.o_wb2_stall(), //1 = busy, cannot accept requests
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.o_wb2_ack(), //1 = read/write request has completed
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.o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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//
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// DDR3 I/O Interface
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.o_ddr3_clk_p(ddr3_clk_p),
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.o_ddr3_clk_n(ddr3_clk_n),
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.o_ddr3_reset_n(ddr3_reset_n),
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.o_ddr3_cke(ddr3_cke), // CKE
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.o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
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.o_ddr3_ras_n(ddr3_ras_n), // RAS#
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.o_ddr3_cas_n(ddr3_cas_n), // CAS#
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.o_ddr3_we_n(ddr3_we_n), // WE#
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.o_ddr3_addr(ddr3_addr),
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.o_ddr3_ba_addr(ddr3_ba),
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.io_ddr3_dq(ddr3_dq),
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.io_ddr3_dqs(ddr3_dqs_p),
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.io_ddr3_dqs_n(ddr3_dqs_n),
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.o_ddr3_dm(ddr3_dm),
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.o_ddr3_odt(ddr3_odt), // on-die termination
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// Debug outputs
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.o_debug1(o_debug1),
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.o_debug2(o_debug2),
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.o_debug3(o_debug3),
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.o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
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.o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
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////////////////////////////////////
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);
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*/
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// Wire connections between controller and phy
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wire[cmd_len*serdes_ratio-1:0] cmd;
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wire dqs_tri_control, dq_tri_control;
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wire toggle_dqs;
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wire[wb_data_bits-1:0] data;
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wire[wb_sel_bits-1:0] dm;
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wire[LANES-1:0] bitslip;
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wire[DQ_BITS*LANES*8-1:0] iserdes_data;
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wire[LANES*8-1:0] iserdes_dqs;
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wire[LANES*8-1:0] iserdes_bitslip_reference;
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wire idelayctrl_rdy;
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wire[4:0] odelay_data_cntvaluein, odelay_dqs_cntvaluein;
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wire[4:0] idelay_data_cntvaluein, idelay_dqs_cntvaluein;
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wire[LANES-1:0] odelay_data_ld, odelay_dqs_ld;
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wire[LANES-1:0] idelay_data_ld, idelay_dqs_ld;
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wire write_leveling_calib;
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wire reset;
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//module instantiations
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ddr3_controller #(
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.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
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.ROW_BITS(ROW_BITS), //width of row address
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.COL_BITS(COL_BITS), //width of column address
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.BA_BITS(BA_BITS), //width of bank address
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.DQ_BITS(DQ_BITS), //width of DQ
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.LANES(LANES), //8 lanes of DQ
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.AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4)
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.WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus
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.WB2_DATA_BITS(WB2_DATA_BITS), //width of 2nd wishbone data bus
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.OPT_LOWPOWER(OPT_LOWPOWER), //1 = low power, 0 = low logic
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.OPT_BUS_ABORT(OPT_BUS_ABORT), //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
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.MICRON_SIM(MICRON_SIM), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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.SECOND_WISHBONE(SECOND_WISHBONE) //set to 1 if 2nd wishbone is needed
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) ddr3_controller_inst (
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.i_controller_clk(i_controller_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD
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.i_rst_n(i_rst_n), //200MHz input clock
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// Wishbone inputs
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.i_wb_cyc(i_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(i_wb_stb), //request a transfer
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.i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col}
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.i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(i_wb_sel), //byte strobe for write (1 = write the byte)
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.i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
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.o_wb_ack(o_wb_ack), //1 = read/write request has completed
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.o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_aux(o_aux), //for AXI-interface compatibility (returned upon ack)
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// Wishbone 2 (PHY) inputs
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.i_wb2_cyc(i_wb2_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb2_stb(i_wb2_stb), //request a transfer
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.i_wb2_we(i_wb2_we), //write-enable (1 = write, 0 = read)
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.i_wb2_addr(i_wb2_addr), // memory-mapped register to be accessed
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.i_wb2_data(i_wb2_data), //write data
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.i_wb2_sel(i_wb2_sel), //byte strobe for write (1 = write the byte)
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// Wishbone 2 (Controller) outputs
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.o_wb2_stall(o_wb2_stall), //1 = busy, cannot accept requests
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.o_wb2_ack(o_wb2_ack), //1 = read/write request has completed
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.o_wb2_data(o_wb2_data), //read data
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//
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// PHY interface
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.i_phy_iserdes_data(iserdes_data),
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.i_phy_iserdes_dqs(iserdes_dqs),
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.i_phy_iserdes_bitslip_reference(iserdes_bitslip_reference),
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.i_phy_idelayctrl_rdy(idelayctrl_rdy),
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.o_phy_cmd(cmd),
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.o_phy_dqs_tri_control(dqs_tri_control),
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.o_phy_dq_tri_control(dq_tri_control),
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.o_phy_toggle_dqs(toggle_dqs),
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.o_phy_data(data),
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.o_phy_dm(dm),
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.o_phy_odelay_data_cntvaluein(odelay_data_cntvaluein),
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.o_phy_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
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.o_phy_idelay_data_cntvaluein(idelay_data_cntvaluein),
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.o_phy_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
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.o_phy_odelay_data_ld(odelay_data_ld),
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.o_phy_odelay_dqs_ld(odelay_dqs_ld),
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.o_phy_idelay_data_ld(idelay_data_ld),
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.o_phy_idelay_dqs_ld(idelay_dqs_ld),
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.o_phy_bitslip(bitslip),
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.o_phy_write_leveling_calib(write_leveling_calib),
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.o_phy_reset(reset),
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// Debug outputs
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.o_debug1(o_debug1),
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.o_debug2(o_debug2),
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.o_debug3(o_debug3)
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);
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ddr3_phy #(
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.ROW_BITS(ROW_BITS), //width of row address
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.BA_BITS(BA_BITS), //width of bank address
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.DQ_BITS(DQ_BITS), //width of DQ
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.LANES(LANES), //8 lanes of DQ
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.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, period of clock input to this DDR3 controller module
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, period of clock input to DDR3 RAM device
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.ODELAY_SUPPORTED(ODELAY_SUPPORTED)
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) ddr3_phy_inst (
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.i_controller_clk(i_controller_clk),
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.i_ddr3_clk(i_ddr3_clk),
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.i_ref_clk(i_ref_clk),
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.i_ddr3_clk_90(i_ddr3_clk_90),
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.i_rst_n(i_rst_n),
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// Controller Interface
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.i_controller_reset(reset),
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.i_controller_cmd(cmd),
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.i_controller_dqs_tri_control(dqs_tri_control),
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.i_controller_dq_tri_control(dq_tri_control),
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.i_controller_toggle_dqs(toggle_dqs),
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.i_controller_data(data),
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.i_controller_dm(dm),
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.i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
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.i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
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.i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
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.i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
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.i_controller_odelay_data_ld(odelay_data_ld),
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.i_controller_odelay_dqs_ld(odelay_dqs_ld),
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.i_controller_idelay_data_ld(idelay_data_ld),
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.i_controller_idelay_dqs_ld(idelay_dqs_ld),
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.i_controller_bitslip(bitslip),
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.i_controller_write_leveling_calib(write_leveling_calib),
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.o_controller_iserdes_data(iserdes_data),
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.o_controller_iserdes_dqs(iserdes_dqs),
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.o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
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.o_controller_idelayctrl_rdy(idelayctrl_rdy),
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// DDR3 I/O Interface
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.o_ddr3_clk_p(o_ddr3_clk_p),
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.o_ddr3_clk_n(o_ddr3_clk_n),
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.o_ddr3_reset_n(o_ddr3_reset_n),
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.o_ddr3_cke(o_ddr3_cke), // CKE
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.o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal
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.o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
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.o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
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.o_ddr3_we_n(o_ddr3_we_n), // WE#
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.o_ddr3_addr(o_ddr3_addr),
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.o_ddr3_ba_addr(o_ddr3_ba_addr),
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.io_ddr3_dq(io_ddr3_dq),
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.io_ddr3_dqs(io_ddr3_dqs),
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.io_ddr3_dqs_n(io_ddr3_dqs_n),
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.o_ddr3_dm(o_ddr3_dm),
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.o_ddr3_odt(o_ddr3_odt), // on-die termination
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.o_ddr3_debug_read_dqs_p(o_ddr3_debug_read_dqs_p),
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.o_ddr3_debug_read_dqs_n(o_ddr3_debug_read_dqs_n)
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);
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endmodule
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