luke
/
UberDDR3
mirror of https://github.com/AngeloJacobo/UberDDR3.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
UberDDR3/sdram_ddr3.txt

385 lines
18 KiB
Plaintext
Raw Blame History

################################################################################
##
## Filename: s dram_ddr3.txt
## {{{
## Project: 10Gb Ethernet switch
##
## Purpose: To describe how to provide access to an SDRAM controller
## from the Wishbone bus, where such SDRAM controller uses a
## different clock from the Wishbone bus itself.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2023, Gisselquist Technology, LLC
## {{{
## This file is part of the ETH10G project.
##
## The ETH10G project contains free software and gateware, licensed under the
## Apache License, Version 2.0 (the "License"). You may not use this project,
## or this file, except in compliance with the License. You may obtain a copy
## of the License at
## }}}
## http://www.apache.org/licenses/LICENSE-2.0
## {{{
## Unless required by applicable law or agreed to in writing, files
## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
## License for the specific language governing permissions and limitations
## under the License.
##
################################################################################
##
## }}}
@PREFIX=sdram_ddr3
@DEVID=SDRAM_DDR3
@ACCESS=@$(DEVID)_ACCESS
## LGMEMSZ is the size of the SDRAM in bytes, 29 => 512MB
@$LGMEMSZ=29
@LGMEMSZ.FORMAT=%d
## UNUSED = log_2(512) = 9
@$UNUSED=9
@$NADDR=(1<<(LGMEMSZ-(@$(UNUSED))))
@$NBYTES=(1<<(@$LGMEMSZ))
@NBYTES.FORMAT=0x%08x
@$MADDR= @$(REGBASE)
@MADDR.FORMAT=0x%08x
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wbwide
@BUS=wbwide
# @CLOCK.NAME=clk
# @CLOCK.FREQUENCY = 81250000
## @ERROR.WIRE=@$(PREFIX)_err
# 8-bit byte accesses
@$ABITS=@$(LGMEMSZ)-@$(UNUSED)
@LD.PERM=wx
@TOP.PORTLIST=
// SDRAM I/O port wires
o_ddr3_reset_n, o_ddr3_cke_n, o_ddr3_clk_p, o_ddr3_clk_n,
o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n,
io_ddr3_dqs_p, io_ddr3_dqs_n,
o_ddr3_a, o_ddr3_ba,
io_ddr3_dq, o_ddr3_dm, o_ddr3_odt
@TOP.IODECL=
// I/O declarations for the DDR3 SDRAM
// {{{
output wire o_ddr3_reset_n;
output wire [0:0] o_ddr3_cke_n;
output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n;
//output wire [0:0] ddr3_cs_n; // This design has no CS pin
output wire o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n;
output wire [2:0] o_ddr3_ba;
output wire [14:0] o_ddr3_a;
output wire [0:0] o_ddr3_odt;
output wire [7:0] o_ddr3_dm;
inout wire [7:0] io_ddr3_dqs_p, io_ddr3_dqs_n;
inout wire [63:0] io_ddr3_dq;
// }}}
@TOP.DEFNS=
// Wires necessary to run the SDRAM
// {{{
wire @$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we,
@$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_err;
wire [(@$(LGMEMSZ)-@$(UNUSED)-1):0] @$(PREFIX)_addr;
wire [(@$(BUS.WIDTH)-1):0] @$(PREFIX)_wdata,
@$(PREFIX)_rdata;
wire [(@$(BUS.WIDTH)/8-1):0] @$(PREFIX)_sel;
// }}}
@TOP.MAIN=
// The SDRAM interface to an toplevel AXI4 module
//
@$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we,
@$(PREFIX)_addr, @$(PREFIX)_wdata, @$(PREFIX)_sel,
@$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_rdata,
@$(PREFIX)_err
@TOP.INSERT=
ddr3_top #(
.ROW_BITS(14), //width of row address
.COL_BITS(10), //width of column address
.BA_BITS(3), //width of bank address
.DQ_BITS(8), //width of DQ
.CONTROLLER_CLK_PERIOD(10), //ns, period of clock input to this DDR3 controller module
.DDR3_CLK_PERIOD(2.5), //ns, period of clock input to DDR3 RAM device
.LANES(8), //8 lanes of DQ
.OPT_LOWPOWER(1), //1 = low power, 0 = low logic
.OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
) @$(PREFIX)_inst(
// {{{
// clock and reset
.i_controller_clk(s_clk),
.i_ddr3_clk(s_clk4x),
.i_ref_clk(s_clk200),
.i_rst_n(!s_reset),
// Wishbone inputs
.i_wb_cyc(@$(PREFIX)_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
.i_wb_stb(@$(PREFIX)_stb), //request a transfer
.i_wb_we(@$(PREFIX)_we), //write-enable (1 = write, 0 = read)
.i_wb_addr(@$(PREFIX)_addr), //burst-addressable {row,bank,col}
.i_wb_data(@$(PREFIX)_wdata), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
.i_wb_sel(@$(PREFIX)_sel), //byte strobe for write (1 = write the byte)
.i_aux(), //for AXI-interface compatibility (given upon strobe)
// Wishbone outputs
.o_wb_stall(@$(PREFIX)_stall), //1 = busy, cannot accept requests
.o_wb_ack(@$(PREFIX)_ack), //1 = read/write request has completed
.o_wb_data(@$(PREFIX)_rdata), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
.o_aux(), //for AXI-interface compatibility (returned upon ack)
// PHY Interface
.o_ddr3_reset_n(o_ddr3_reset_n),
.o_ddr3_cke(o_ddr3_cke_n), // CKE
.o_ddr3_cs_n(), // chip select signal
.o_ddr3_ras_n(o_ddr3_ras_n),
.o_ddr3_cas_n(o_ddr3_cas_n),
.o_ddr3_we_n(o_ddr3_we_n),
.o_ddr3_addr(o_ddr3_a),
.o_ddr3_ba_addr(o_ddr3_ba),
.io_ddr3_dq(io_ddr3_dq),
.io_ddr3_dqs(io_ddr3_dqs_p),
.io_ddr3_dqs_n(io_ddr3_dqs_n),
.o_ddr3_odt(o_ddr3_odt) // on-die termination
// }}}
);
@MAIN.PORTLIST=
// SDRAM ports
o_@$(PREFIX)_cyc, o_@$(PREFIX)_stb, o_@$(PREFIX)_we,
o_@$(PREFIX)_addr, o_@$(PREFIX)_data, o_@$(PREFIX)_sel,
i_@$(PREFIX)_stall, i_@$(PREFIX)_ack, i_@$(PREFIX)_data,
i_@$(PREFIX)_err
@MAIN.IODECL=
// SDRAM I/O declarations
// {{{
output wire o_@$(PREFIX)_cyc,
o_@$(PREFIX)_stb, o_@$(PREFIX)_we;
output wire [@$(ABITS)-1:0] o_@$(PREFIX)_addr;
output wire [(@$(BUS.WIDTH)-1):0] o_@$(PREFIX)_data;
output wire [(@$(BUS.WIDTH)/8)-1:0] o_@$(PREFIX)_sel;
//
input wire i_@$(PREFIX)_ack;
input wire i_@$(PREFIX)_stall;
input wire [(@$(BUS.WIDTH)-1):0] i_@$(PREFIX)_data;
// Verilator lint_off UNUSED
input wire i_@$(PREFIX)_err;
// Verilator lint_on UNUSED
// }}}
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// Export the @$(PREFIX) bus to the top level
// {{{
assign o_@$(PREFIX)_cyc = @$(SLAVE.PREFIX)_cyc;
assign o_@$(PREFIX)_stb =(@$(SLAVE.PREFIX)_stb);
assign o_@$(PREFIX)_we = @$(SLAVE.PREFIX)_we;
assign o_@$(PREFIX)_addr = @$(SLAVE.PREFIX)_addr[@$(ABITS)-1:0];
assign o_@$(PREFIX)_data = @$(SLAVE.PREFIX)_data;
assign o_@$(PREFIX)_sel = @$(SLAVE.PREFIX)_sel;
assign @$(SLAVE.PREFIX)_ack = i_@$(PREFIX)_ack;
assign @$(SLAVE.PREFIX)_stall = i_@$(PREFIX)_stall;
assign @$(SLAVE.PREFIX)_idata = i_@$(PREFIX)_data;
// }}}
@REGS.N=1
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$(NBYTES)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES];
@SIM.INCLUDE=
#include "memsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
MEMSIM *m_@$(PREFIX);
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(PREFIX) = new MEMSIM(@$(NBYTES));
#endif // @$(ACCESS)
@SIM.CLOCK=@$(SLAVE.BUS.CLOCK.NAME)
@SIM.TICK=
#ifdef @$(ACCESS)
// Simulate the SDRAM
// {{{
(*m_@$(PREFIX))(m_core->o_@$(PREFIX)_cyc,
m_core->o_@$(PREFIX)_stb,
m_core->o_@$(PREFIX)_we,
m_core->o_@$(PREFIX)_addr,
&m_core->o_@$(PREFIX)_data,
m_core->o_@$(PREFIX)_sel,
m_core->i_@$(PREFIX)_stall,
m_core->i_@$(PREFIX)_ack,
&m_core->i_@$(PREFIX)_data);
m_core->i_@$(PREFIX)_err = 0;
// }}}
#endif // @$(ACCESS)
@SIM.LOAD=
m_@$(PREFIX)->load(start, &buf[offset], wlen);
@XDC.INSERT=
## DDR3
## {{{
set_property -dict {PACKAGE_PIN V11 IOSTANDARD SSTL15} [get_ports o_ddr3_reset_n]
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD SSTL15} [get_ports o_ddr3_clk_p]
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD SSTL15} [get_ports o_ddr3_clk_n]
#set_property -dict {PACKAGE_PIN AA9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_p[1]]
#set_property -dict {PACKAGE_PIN AB9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_n[1]]
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD SSTL15} [get_ports o_ddr3_cke_n]
#set_property -dict {PACKAGE_PIN W9 IOSTANDARD SSTL15} [get_ports o_ddr3_cke_n[1]]
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD SSTL15} [get_ports o_ddr3_ras_n]
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD SSTL15} [get_ports o_ddr3_cas_n]
set_property -dict {PACKAGE_PIN Y7 IOSTANDARD SSTL15} [get_ports o_ddr3_we_n]
#set_property -dict {PACKAGE_PIN V7 IOSTANDARD SSTL15} [get_ports o_ddr3_s[0]]
#set_property -dict {PACKAGE_PIN Y8 IOSTANDARD SSTL15} [get_ports o_ddr3_s[1]]
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD SSTL15} [get_ports o_ddr3_odt]
#set_property -dict {PACKAGE_PIN V9 IOSTANDARD SSTL15} [get_ports o_ddr3_odt[1]
#set_property -dict {PACKAGE_PIN W10 IOSTANDARD SSTL15} [get_ports i_ddr3_event]
### Address lines
### {{{
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[0]]
set_property -dict {PACKAGE_PIN V8 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[1]]
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[2]]
set_property -dict {PACKAGE_PIN AF7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[0]]
set_property -dict {PACKAGE_PIN AD8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[1]]
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD SSTL15} [get_ports o_ddr3_a[2]]
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[3]]
set_property -dict {PACKAGE_PIN W11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[4]]
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[5]]
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[6]]
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[7]]
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[8]]
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[9]]
set_property -dict {PACKAGE_PIN AE7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[10]]
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[11]]
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[12]]
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[13]]
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[14]]
#set_property -dict {PACKAGE_PIN Y12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[15]]
### }}}
### Byte lane #0
### {{{
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[0]]
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[1]]
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[2]]
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[3]]
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[4]]
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[5]]
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[6]]
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[7]]
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[0]]
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[0]]
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[0]]
### }}}
### Byte lane #1
### {{{
set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[8]]
set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[9]]
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[10]]
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[11]]
set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[12]]
set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[13]]
set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[14]]
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[15]]
set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[1]]
set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[1]]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[1]]
### }}}
### Byte lane #2
### {{{
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[16]]
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[17]]
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[18]]
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[19]]
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[20]]
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[21]]
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[22]]
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[23]]
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[2]]
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[2]]
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[2]]
### }}}
### Byte lane #3
### {{{
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[24]]
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[25]]
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[26]]
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[27]]
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[28]]
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[29]]
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[30]]
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[31]]
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[3]]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[3]]
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[3]]
### }}}
### Byte lane #4
### {{{
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[32]]
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[33]]
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[34]]
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[35]]
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[36]]
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[37]]
set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[38]]
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[39]]
set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[4]]
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[4]]
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[4]]
### }}}
### Byte lane #5
### {{{
set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[40]]
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[41]]
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[42]]
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[43]]
set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[44]]
set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[45]]
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[46]]
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[47]]
set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[5]]
set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[5]]
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[5]]
### }}}
### Byte lane #6
### {{{
set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[48]]
set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[49]]
set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[50]]
set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[51]]
set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[52]]
set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[53]]
set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[54]]
set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[55]]
set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[6]]
set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[6]]
set_property -dict {PACKAGE_PIN U7 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[6]]
### }}}
### Byte lane #7
### {{{
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[56]]
set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[57]]
set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[58]]
set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[59]]
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[60]]
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[61]]
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[62]]
set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[63]]
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[7]]
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[7]]
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[7]]
### }}}
Reference in New Issue View Git Blame Copy Permalink