91 lines
2.2 KiB
Plaintext
91 lines
2.2 KiB
Plaintext
[*]
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[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
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[*] Tue Jun 27 09:57:53 2023
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[*]
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[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace0.vcd"
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[dumpfile_mtime] "Tue Jun 27 08:16:33 2023"
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[dumpfile_size] 370354
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[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/new_formal.gtkw"
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[timestart] 167
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[size] 1848 1126
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[pos] -51 -51
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*-4.943873 244 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 369
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[signals_width] 430
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[sst_expanded] 1
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[sst_vpaned_height] 743
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@420
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smt_step
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@28
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ddr3_controller.i_controller_clk
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ddr3_controller.i_rst_n
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@24
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ddr3_controller.state_calibrate[3:0]
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ddr3_controller.instruction_address[4:0]
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@28
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ddr3_controller.reset_done
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@200
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-
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-WB Interface
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@28
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ddr3_controller.i_wb_cyc
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ddr3_controller.o_wb_stall
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ddr3_controller.i_wb_stb
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ddr3_controller.i_wb_we
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@22
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ddr3_controller.i_wb_addr[23:0]
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ddr3_controller.i_wb_data[511:0]
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ddr3_controller.i_wb_sel[63:0]
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@28
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ddr3_controller.o_wb_ack
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@200
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-
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-Internals
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@28
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ddr3_controller.stage1_pending
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ddr3_controller.stage1_we
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@24
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ddr3_controller.stage1_bank[2:0]
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ddr3_controller.stage1_col[9:0]
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@25
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ddr3_controller.stage1_row[13:0]
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@24
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ddr3_controller.stage1_stall
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@204
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-
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@24
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ddr3_controller.stage2_pending
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ddr3_controller.stage2_we
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ddr3_controller.stage2_bank[2:0]
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ddr3_controller.stage2_col[9:0]
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ddr3_controller.stage2_row[13:0]
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ddr3_controller.stage2_stall
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@200
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-
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@28
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ddr3_controller.bank_status_q[7:0]
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@22
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ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
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ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
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ddr3_controller.delay_before_activate_counter_q<1>[3:0]
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ddr3_controller.delay_before_activate_counter_q<2>[3:0]
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ddr3_controller.delay_before_read_counter_q<1>[3:0]
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ddr3_controller.delay_before_read_counter_q<2>[3:0]
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ddr3_controller.delay_before_write_counter_q<1>[3:0]
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ddr3_controller.delay_before_write_counter_q<2>[3:0]
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@200
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-
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-CMD
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@28
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+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
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+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
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+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
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+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
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@200
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-
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-Formal
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@24
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ddr3_controller.f_index[4:0]
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[pattern_trace] 1
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[pattern_trace] 0
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