14773 lines
2.2 MiB
14773 lines
2.2 MiB
start_gui
|
|
open_project /home/angelo/Desktop/switch_fpga/switch_fpga.xpr
|
|
open_project /home/angelo/Desktop/switch_fpga/switch_fpga.xpr
|
|
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/angelo/Desktop/switch_fpga/switch_fpga.gen/sources_1'.
|
|
Scanning sources...
|
|
Finished scanning sources
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2021.2/data/ip'.
|
|
open_project: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 7512.031 ; gain = 60.039 ; free physical = 998 ; free virtual = 24986
|
|
update_compile_order -fileset sources_1
|
|
launch_simulation
|
|
Command: launch_simulation
|
|
INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim'
|
|
WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
|
|
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
|
|
INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
INFO: [SIM-utils-72] Using boost library from '/tools/Xilinx/Vivado/2021.2/tps/boost_1_72_0'
|
|
INFO: [SIM-utils-54] Inspecting design source files for 'ddr3_dimm_micron_sim' in fileset 'sim_1'...
|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
|
|
INFO: [USF-XSim-2] XSim::Compile design
|
|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
|
|
xvlog --incr --relax -L uvm -prj ddr3_dimm_micron_sim_vlog.prj
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module ddr3_controller
|
|
WARNING: [VRFC 10-3380] identifier 'PRECHARGE_TO_ACTIVATE_DELAY' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:187]
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module ddr3_phy
|
|
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:273]
|
|
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:318]
|
|
WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:365]
|
|
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module ddr3_top
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module ddr3
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module ddr3_dimm
|
|
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
|
|
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
|
|
Waiting for jobs to finish...
|
|
No pending jobs, compilation finished.
|
|
run_program: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 7565.305 ; gain = 0.000 ; free physical = 837 ; free virtual = 24958
|
|
INFO: [USF-XSim-69] 'compile' step finished in '11' seconds
|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
|
|
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
|
Vivado Simulator v2021.2
|
|
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
|
|
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
|
Using 8 slave threads.
|
|
Starting static elaboration
|
|
Pass Through NonSizing Optimizer
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:197]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:128]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:149]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:150]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:151]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:152]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:153]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:154]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:243]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:269]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:270]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:277]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:313]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:320]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:372]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:373]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:419]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:420]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:421]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:423]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:428]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:502]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:505]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:553]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:554]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:622]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:623]
|
|
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:669]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:157]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:158]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:159]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:160]
|
|
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
|
|
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
|
|
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:167]
|
|
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:168]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
|
|
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
|
|
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:155]
|
|
Completed static elaboration
|
|
Starting simulation data flow analysis
|
|
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
|
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller_default doesn't have a timescale but at least one module in design has a timescale.
|
|
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
|
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
|
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller_default doesn't have a timescale but at least one module in design has a timescale.
|
|
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
|
|
Completed simulation data flow analysis
|
|
Time Resolution for simulation is 1ps
|
|
Compiling module xil_defaultlib.ddr3_controller_default
|
|
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
|
|
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
|
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
|
|
Compiling module unisims_ver.OBUFDS
|
|
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
|
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
|
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
|
|
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
|
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
|
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
|
|
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
|
|
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
|
|
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
|
|
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
|
|
Compiling module unisims_ver.IDELAYCTRL_default
|
|
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
|
|
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
|
|
Compiling module xil_defaultlib.ddr3_default
|
|
Compiling module xil_defaultlib.ddr3_dimm_default
|
|
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
|
|
Compiling module xil_defaultlib.glbl
|
|
Built simulation snapshot ddr3_dimm_micron_sim_behav
|
|
run_program: Time (s): cpu = 00:02:44 ; elapsed = 00:02:08 . Memory (MB): peak = 7565.305 ; gain = 0.000 ; free physical = 1239 ; free virtual = 24635
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '128' seconds
|
|
INFO: [USF-XSim-4] XSim::Simulate design
|
|
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
|
|
INFO: [USF-XSim-98] *** Running xsim
|
|
with args "ddr3_dimm_micron_sim_behav -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch {ddr3_dimm_micron_sim.tcl} -view {/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_dimm_micron_sim_behav.wcfg} -log {simulate.log}"
|
|
INFO: [USF-XSim-8] Loading simulator feature
|
|
Time resolution is 1 ps
|
|
open_wave_config /home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_dimm_micron_sim_behav.wcfg
|
|
source ddr3_dimm_micron_sim.tcl
|
|
# set curr_wave [current_wave_config]
|
|
# if { [string length $curr_wave] == 0 } {
|
|
# if { [llength [get_objects]] > 0} {
|
|
# add_wave /
|
|
# set_property needs_save false [current_wave_config]
|
|
# } else {
|
|
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
|
# }
|
|
# }
|
|
# run 1000ns
|
|
Test ns_to_cycles() function:
|
|
ns_to_cycles(15) = 3 = 2 [exact]
|
|
ns_to_cycles(14.5) = 3 = 2 [round-off]
|
|
ns_to_cycles(11) = 3 = 2 [round-up]
|
|
|
|
Test nCK_to_cycles() function:
|
|
ns_to_cycles(16) = 4 = 4 [exact]
|
|
ns_to_cycles(15) = 4 = 4 [round-off]
|
|
ns_to_cycles(13) = 4 = 4 [round-up]
|
|
|
|
Test ns_to_nCK() function:
|
|
ns_to_cycles(15) = 12 = 6 [exact]
|
|
ns_to_cycles(14.875) = 12 = 6 [round-off]
|
|
ns_to_cycles(13.875) = 12 = 6 [round-up]
|
|
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
|
|
tRTP = 7.5 = 10.000000
|
|
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
|
|
|
|
Test nCK_to_ns() function:
|
|
ns_to_cycles(4) = 5 = 10 [exact]
|
|
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
|
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
|
|
|
Test nCK_to_ns() function:
|
|
ns_to_cycles(4) = 5 = 10 [exact]
|
|
ns_to_cycles(14.875) = 4 = 8 [round-off]
|
|
ns_to_cycles(13.875) = 7 = 13 [round-up]
|
|
|
|
Test $floor() function:
|
|
$floor(5/2) = 2.5 = 2
|
|
$floor(9/4) = 2.25 = 2
|
|
$floor(9/4) = 2 = 2
|
|
$floor(9/5) = 1.8 = 1
|
|
|
|
|
|
DELAY_COUNTER_WIDTH = 16
|
|
DELAY_SLOT_WIDTH = 19
|
|
serdes_ratio = 4
|
|
wb_addr_bits = 24
|
|
wb_data_bits = 512
|
|
wb_sel_bits = 64
|
|
|
|
|
|
READ_SLOT = 2
|
|
WRITE_SLOT = 3
|
|
ACTIVATE_SLOT = 0
|
|
PRECHARGE_SLOT = 1
|
|
|
|
|
|
DELAYS:
|
|
ns_to_nCK(tRCD): 6
|
|
ns_to_nCK(tRP): 6
|
|
ns_to_nCK(tRTP): 4
|
|
tCCD: 4
|
|
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
|
|
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
|
|
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
|
|
$signed(4'b1100)>>>4: 1111
|
|
|
|
|
|
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
|
|
ACTIVATE_TO_WRITE_DELAY = 3 = 0
|
|
ACTIVATE_TO_READ_DELAY = 2 = 0
|
|
READ_TO_WRITE_DELAY = 2 = 1
|
|
READ_TO_READ_DELAY = 0 = 0
|
|
READ_TO_PRECHARGE_DELAY = 1 =1
|
|
WRITE_TO_WRITE_DELAY = 0 = 0
|
|
WRITE_TO_READ_DELAY = 4 = 3
|
|
WRITE_TO_PRECHARGE_DELAY = 5 = 4
|
|
STAGE2_DATA_DEPTH = 2 = 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
[x ps] MRS -> [ 2500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 291324.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
[190000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 802600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
[510000 ps] NOP -> run: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 7628.176 ; gain = 2.000 ; free physical = 900 ; free virtual = 24441
|
|
xsim: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 7628.176 ; gain = 53.836 ; free physical = 900 ; free virtual = 24441
|
|
INFO: [USF-XSim-96] XSim completed. Design snapshot 'ddr3_dimm_micron_sim_behav' loaded.
|
|
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
|
|
launch_simulation: Time (s): cpu = 00:03:08 ; elapsed = 00:02:40 . Memory (MB): peak = 7628.176 ; gain = 62.871 ; free physical = 900 ; free virtual = 24441
|
|
run all
|
|
[370000 ps] MRS ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
|
|
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[237500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43451402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43453902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43456402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43458902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43461402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43463902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43466402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43468902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43601480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43603980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43606480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43608980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43611480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43613980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43616480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43618980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45552600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45555100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45557600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45560100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45562600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45565100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45567600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45570100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45702600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45705100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45707600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45710100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45712600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45715100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45717600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45720100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46301402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46303902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46306402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46308902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46311402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46313902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46316402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46318902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46451480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46453980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46456480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46458980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46461480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46463980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46466480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46468980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48402600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48405100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48407600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48410100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48412600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48415100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48417600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48420100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48552600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48555100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48557600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48560100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48562600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48565100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48567600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48570100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49151402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49153902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49156402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49158902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49161402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49163902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49166402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49168902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49301480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49303980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49306480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49308980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49311480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49313980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49316480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49318980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51252600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51255100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51257600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51260100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51262600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51265100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51267600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51270100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51402600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51405100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51407600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51410100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51412600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51415100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51417600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51420100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52001402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52003902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52006402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52008902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52011402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52013902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52016402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52018902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52151480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52153980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52156480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52158980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52161480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52163980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52166480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52168980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54102600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54105100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54107600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54110100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54112600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54115100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54117600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54120100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54252600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54255100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54257600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54260100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54262600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54265100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54267600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54270100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54851402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54853902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54856402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54858902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54861402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54863902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54866402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54868902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55001480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55003980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55006480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55008980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55011480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55013980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55016480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55018980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56952600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56955100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56957600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56960100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56962600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56965100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56967600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56970100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57102600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57105100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57107600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57110100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57112600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57115100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57117600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57120100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57701402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57703902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57706402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57708902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57711402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57713902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57716402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57718902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57851480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57853980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57856480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57858980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57861480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57863980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57866480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57868980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59802600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59805100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59807600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59810100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59812600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59815100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59817600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59820100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59952600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59955100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59957600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59960100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59962600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59965100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59967600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59970100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60401350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60403850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60406350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60408850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60551350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60551402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60553850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60553902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60556350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60556402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60558850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60558902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60561402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60563902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60566402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60568902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60701350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60701480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60703850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60703980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60706350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60706480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60708850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60708980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60711480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60713980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60716480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60718980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60851350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60853850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60856350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60858850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61001350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61003850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61006350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61008850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61151350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61153850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61156350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61158850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61301350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61303850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61306350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61308850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61451350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61453850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61456350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61458850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61601350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61603850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61606350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61608850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61751350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61753850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61756350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61758850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61901350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61903850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61906350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61908850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62051350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62053850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62056350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62058850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62201350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62203850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62206350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62208850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62351350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62353850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62356350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62358850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62501350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62503850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62506350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62508850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62651350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62652600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62653850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62655100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62656350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62657600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62658850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62660100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62662600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62665100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62667600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62670100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62801350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62802600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62803850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62805100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62806350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62807600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62808850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62810100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62812600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62815100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62817600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62820100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62951350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62952650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62953850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62955150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62956350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62957650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62958850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62960150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63101350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63102650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63103850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63105150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63106350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63107650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63108850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63110150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63251350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63252650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63253850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63255150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63256350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63257650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63258850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63260150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63401402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63402650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63403902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63405150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63406402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63407650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63408902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63410150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63411402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63413902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63416402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63418902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63551480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63552650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63553980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63555150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63556480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63557650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63558980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63560150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63561480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63563980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63566480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63568980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63702650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63705150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63707650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63710150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63852650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63855150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63857650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63860150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64002650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64005150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64007650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64010150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64152650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64155150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64157650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64160150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64302650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64305150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64307650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64310150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64452650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64455150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64457650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64460150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64602650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64605150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64607650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64610150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64752650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64755150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64757650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64760150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64902650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64905150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64907650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64910150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65052650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65055150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65057650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65060150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65202650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65205150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65207650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65210150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65352650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65355150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65357650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65360150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65502600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65502650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65505100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65505150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65507600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65507650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65510100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65510150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65512600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65515100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65517600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65520100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65652600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65652650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65655100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65655150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65657600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65657650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65660100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65660150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65662600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65665100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65667600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65670100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65802650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65805150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65807650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65810150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
|
|
|
|
[22660000 ps] MRS ->
|
|
[10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 0) ->
|
|
[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [192500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
|
|
[20000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
|
|
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
|
|
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
|
|
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
|
|
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
|
|
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
|
|
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
|
|
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
|
|
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
|
|
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
|
|
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
|
|
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
|
|
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
|
|
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
|
|
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
|
|
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
|
|
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
|
|
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
|
|
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
|
|
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
|
|
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
|
|
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
|
|
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
|
|
[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
|
|
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
|
|
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
|
|
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
|
|
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
|
|
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
|
|
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
|
|
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
|
|
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
|
|
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
|
|
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
|
|
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
|
|
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
|
|
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
|
|
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
|
|
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
|
|
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
|
|
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
|
|
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
|
|
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
|
|
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
|
|
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
|
|
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
|
|
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
|
|
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
|
|
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) ->
|
|
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
|
|
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
|
|
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
|
|
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
|
|
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
|
|
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
|
|
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
|
|
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
|
|
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
|
|
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
|
|
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
|
|
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
|
|
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
|
|
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
|
|
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
|
|
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
|
|
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
|
|
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
|
|
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
|
|
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
|
|
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
|
|
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
|
|
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
|
|
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
|
|
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
|
|
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) ->
|
|
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
|
|
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
|
|
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
|
|
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
|
|
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
|
|
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
|
|
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
|
|
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
|
|
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
|
|
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
|
|
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
|
|
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
|
|
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
|
|
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
|
|
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
|
|
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
|
|
[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
|
|
[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
|
|
[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
|
|
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
|
|
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
|
|
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
|
|
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
|
|
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
|
|
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
|
|
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
|
|
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
|
|
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
|
|
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
|
|
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
|
|
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
|
|
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
|
|
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
|
|
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
|
|
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
|
|
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
|
|
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
|
|
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
|
|
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
|
|
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
|
|
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
|
|
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
|
|
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
|
|
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
|
|
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
|
|
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
|
|
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
|
|
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
|
|
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
|
|
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
|
|
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
|
|
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
|
|
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
|
|
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
|
|
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
|
|
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
|
|
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
|
|
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
|
|
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
|
|
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
|
|
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
|
|
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
|
|
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
|
|
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
|
|
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
|
|
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
|
|
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
|
|
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
|
|
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
|
|
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
|
|
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
|
|
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
|
|
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
|
|
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
|
|
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) ->
|
|
[ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [145000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) ->
|
|
[20000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
|
|
[ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
|
|
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
|
|
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
|
|
[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) ->
|
|
[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
|
|
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
|
|
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
|
|
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
|
|
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
|
|
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
|
|
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
|
|
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
|
|
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
|
|
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
|
|
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
|
|
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
|
|
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
|
|
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
|
|
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
|
|
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
|
|
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
|
|
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
|
|
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
|
|
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
|
|
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
|
|
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) ->
|
|
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
|
|
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
|
|
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
|
|
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
|
|
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
|
|
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
|
|
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
|
|
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
|
|
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
|
|
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
|
|
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
|
|
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
|
|
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
|
|
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
|
|
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
|
|
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
|
|
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
|
|
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
|
|
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
|
|
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
|
|
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
|
|
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
|
|
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
|
|
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
|
|
[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
|
|
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) ->
|
|
[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
|
|
[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
|
|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
|
|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
|
|
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
|
|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
|
|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
|
|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
|
|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
|
|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
|
|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
|
|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
|
|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
|
|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
|
|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
|
|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
|
|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
|
|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
|
|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [20000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
|
|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
|
|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
|
|
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
|
|
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
|
|
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
|
|
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
|
|
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
|
|
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
|
|
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
|
|
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
|
|
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
|
|
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
|
|
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
|
|
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
|
|
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
|
|
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
|
|
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
|
|
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
|
|
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
|
|
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
|
|
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
|
|
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
|
|
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
|
|
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
|
|
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
|
|
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
|
|
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) ->
|
|
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
|
|
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
|
|
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
|
|
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
|
|
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
|
|
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
|
|
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
|
|
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
|
|
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
|
|
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
|
|
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
|
|
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
|
|
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
|
|
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
|
|
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
|
|
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
|
|
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
|
|
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
|
|
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
|
|
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
|
|
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
|
|
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
|
|
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
|
|
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
|
|
[ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [147500 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (2, 0) -> [15000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) ->
|
|
[20000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
|
|
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
|
|
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
|
|
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
|
|
[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) ->
|
|
[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
|
|
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
|
|
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
|
|
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
|
|
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
|
|
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
|
|
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
|
|
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
|
|
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
|
|
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
|
|
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
|
|
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
|
|
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
|
|
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
|
|
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
|
|
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
|
|
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
|
|
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
|
|
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
|
|
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
|
|
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
|
|
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
|
|
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
|
|
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
|
|
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
|
|
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
|
|
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
|
|
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
|
|
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
|
|
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
|
|
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
|
|
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
|
|
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
|
|
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
|
|
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
|
|
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
|
|
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
|
|
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
|
|
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
|
|
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
|
|
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
|
|
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
|
|
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
|
|
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
|
|
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
|
|
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
|
|
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
|
|
[ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
|
|
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
|
|
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
|
|
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
|
|
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
|
|
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
|
|
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
|
|
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
|
|
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
|
|
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
|
|
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
|
|
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
|
|
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
|
|
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
|
|
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
|
|
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
|
|
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
|
|
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
|
|
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
|
|
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
|
|
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
|
|
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
|
|
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
|
|
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
|
|
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
|
|
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) ->
|
|
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
|
|
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
|
|
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
|
|
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
|
|
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
|
|
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
|
|
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
|
|
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
|
|
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
|
|
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
|
|
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
|
|
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
|
|
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
|
|
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
|
|
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
|
|
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
|
|
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
|
|
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
|
|
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
|
|
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
|
|
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
|
|
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
|
|
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
|
|
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
|
|
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
|
|
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) ->
|
|
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
|
|
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
|
|
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
|
|
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
|
|
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
|
|
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
|
|
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
|
|
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
|
|
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
|
|
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
|
|
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
|
|
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
|
|
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
|
|
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
|
|
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
|
|
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
|
|
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
|
|
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
|
|
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
|
|
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
|
|
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
|
|
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
|
|
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
|
|
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
|
|
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
|
|
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
|
|
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
|
|
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
|
|
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
|
|
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
|
|
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
|
|
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
|
|
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
|
|
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
|
|
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
|
|
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
|
|
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
|
|
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
|
|
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
|
|
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
|
|
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
|
|
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
|
|
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
|
|
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
|
|
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
|
|
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
|
|
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
|
|
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
|
|
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
|
|
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
|
|
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
|
|
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [10000 ps] RD @ (0, 992) ->
|
|
|
|
DONE TEST 1: FIRST ROW
|
|
|
|
[10000 ps] RD @ (0, 1000) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [157500 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
|
|
[20000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
|
|
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
|
|
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
|
|
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
|
|
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
|
|
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
|
|
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
|
|
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
|
|
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
|
|
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
|
|
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
|
|
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
|
|
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
|
|
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
|
|
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
|
|
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
|
|
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
|
|
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
|
|
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
|
|
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
|
|
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
|
|
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
|
|
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
|
|
[ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
|
|
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
|
|
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
|
|
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
|
|
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
|
|
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
|
|
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
|
|
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
|
|
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
|
|
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
|
|
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
|
|
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
|
|
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
|
|
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
|
|
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
|
|
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
|
|
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
|
|
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
|
|
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
|
|
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
|
|
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
|
|
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
|
|
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
|
|
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
|
|
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
|
|
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) ->
|
|
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
|
|
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
|
|
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
|
|
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
|
|
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
|
|
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
|
|
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
|
|
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
|
|
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
|
|
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
|
|
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
|
|
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
|
|
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
|
|
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
|
|
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
|
|
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
|
|
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
|
|
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
|
|
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
|
|
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
|
|
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
|
|
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
|
|
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
|
|
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
|
|
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
|
|
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) ->
|
|
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
|
|
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
|
|
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
|
|
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
|
|
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
|
|
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
|
|
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
|
|
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
|
|
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
|
|
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
|
|
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
|
|
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
|
|
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
|
|
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
|
|
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
|
|
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
|
|
[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
|
|
[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
|
|
[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
|
|
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
|
|
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
|
|
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
|
|
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
|
|
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
|
|
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
|
|
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
|
|
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
|
|
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
|
|
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
|
|
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
|
|
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
|
|
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
|
|
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
|
|
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
|
|
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
|
|
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
|
|
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
|
|
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
|
|
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
|
|
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
|
|
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
|
|
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
|
|
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
|
|
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
|
|
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
|
|
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
|
|
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
|
|
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
|
|
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
|
|
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
|
|
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
|
|
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
|
|
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
|
|
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
|
|
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
|
|
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
|
|
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
|
|
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
|
|
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
|
|
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
|
|
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
|
|
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
|
|
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
|
|
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
|
|
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
|
|
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
|
|
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
|
|
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
|
|
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
|
|
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
|
|
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
|
|
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
|
|
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
|
|
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
|
|
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) ->
|
|
[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) ->
|
|
[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
|
|
[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
|
|
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
|
|
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
|
|
[ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [145000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) ->
|
|
[20000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
|
|
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
|
|
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
|
|
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
|
|
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
|
|
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
|
|
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
|
|
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
|
|
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
|
|
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
|
|
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
|
|
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
|
|
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
|
|
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
|
|
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
|
|
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
|
|
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
|
|
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
|
|
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
|
|
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
|
|
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
|
|
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) ->
|
|
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
|
|
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
|
|
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
|
|
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
|
|
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
|
|
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
|
|
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
|
|
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
|
|
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
|
|
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
|
|
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
|
|
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
|
|
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
|
|
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
|
|
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
|
|
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
|
|
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
|
|
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
|
|
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
|
|
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
|
|
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
|
|
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
|
|
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
|
|
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
|
|
[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
|
|
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) ->
|
|
[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
|
|
[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
|
|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
|
|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
|
|
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
|
|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
|
|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
|
|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
|
|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
|
|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
|
|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
|
|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
|
|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
|
|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
|
|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
|
|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
|
|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
|
|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
|
|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [20000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
|
|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
|
|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
|
|
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
|
|
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
|
|
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
|
|
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
|
|
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
|
|
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
|
|
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
|
|
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
|
|
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
|
|
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
|
|
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
|
|
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
|
|
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
|
|
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
|
|
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
|
|
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
|
|
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
|
|
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
|
|
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
|
|
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
|
|
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
|
|
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
|
|
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
|
|
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
|
|
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) ->
|
|
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
|
|
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
|
|
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
|
|
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
|
|
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
|
|
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
|
|
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
|
|
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
|
|
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
|
|
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
|
|
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
|
|
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
|
|
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
|
|
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
|
|
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
|
|
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
|
|
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
|
|
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
|
|
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
|
|
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
|
|
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
|
|
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
|
|
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
|
|
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
|
|
[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) ->
|
|
[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
|
|
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
|
|
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
|
|
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
|
|
[ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [147500 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) ->
|
|
[20000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
|
|
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
|
|
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
|
|
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
|
|
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
|
|
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
|
|
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
|
|
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
|
|
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
|
|
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
|
|
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
|
|
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
|
|
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
|
|
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
|
|
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
|
|
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
|
|
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
|
|
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
|
|
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
|
|
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
|
|
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
|
|
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
|
|
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
|
|
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
|
|
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
|
|
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
|
|
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
|
|
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
|
|
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
|
|
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
|
|
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
|
|
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
|
|
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
|
|
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
|
|
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
|
|
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
|
|
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
|
|
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
|
|
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
|
|
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
|
|
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
|
|
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
|
|
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
|
|
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
|
|
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
|
|
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
|
|
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
|
|
[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
|
|
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
|
|
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
|
|
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
|
|
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
|
|
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
|
|
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
|
|
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
|
|
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
|
|
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
|
|
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
|
|
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
|
|
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
|
|
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
|
|
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
|
|
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
|
|
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
|
|
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
|
|
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
|
|
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
|
|
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
|
|
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
|
|
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
|
|
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
|
|
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
|
|
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) ->
|
|
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
|
|
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
|
|
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
|
|
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
|
|
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
|
|
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
|
|
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
|
|
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
|
|
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
|
|
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
|
|
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
|
|
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
|
|
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
|
|
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
|
|
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
|
|
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
|
|
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
|
|
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
|
|
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
|
|
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
|
|
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
|
|
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
|
|
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
|
|
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
|
|
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
|
|
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) ->
|
|
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
|
|
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
|
|
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
|
|
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
|
|
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
|
|
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
|
|
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
|
|
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
|
|
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
|
|
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
|
|
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
|
|
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
|
|
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
|
|
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
|
|
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
|
|
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
|
|
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
|
|
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
|
|
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
|
|
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
|
|
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
|
|
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
|
|
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
|
|
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
|
|
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
|
|
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
|
|
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
|
|
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
|
|
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
|
|
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
|
|
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
|
|
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
|
|
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
|
|
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
|
|
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
|
|
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
|
|
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
|
|
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
|
|
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
|
|
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
|
|
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
|
|
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
|
|
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
|
|
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
|
|
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
|
|
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
|
|
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
|
|
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
|
|
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
|
|
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
|
|
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
|
|
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [10000 ps] RD @ (0, 992) ->
|
|
|
|
DONE TEST 1: MIDDLE ROW
|
|
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [107500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) ->
|
|
[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [20000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
|
|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 64) ->
|
|
[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [145000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[27500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [20000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
|
|
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
|
|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
|
|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
|
|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
|
|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
|
|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
|
|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
|
|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
|
|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
|
|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
|
|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
|
|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
|
|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
|
|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
|
|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) ->
|
|
[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) ->
|
|
[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) ->
|
|
[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) ->
|
|
[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) ->
|
|
[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) ->
|
|
[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) ->
|
|
[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) ->
|
|
[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) ->
|
|
[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) ->
|
|
[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) ->
|
|
[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) ->
|
|
[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) ->
|
|
[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) ->
|
|
[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) ->
|
|
[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) ->
|
|
[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) ->
|
|
[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) ->
|
|
[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) ->
|
|
[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) ->
|
|
[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) ->
|
|
[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) ->
|
|
[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) ->
|
|
[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) ->
|
|
[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) ->
|
|
[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) ->
|
|
[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) ->
|
|
[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) ->
|
|
[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) ->
|
|
[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) ->
|
|
[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) ->
|
|
[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) ->
|
|
[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) ->
|
|
[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) ->
|
|
[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) ->
|
|
[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) ->
|
|
[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) ->
|
|
[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) ->
|
|
[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) ->
|
|
[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) ->
|
|
[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) ->
|
|
[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) ->
|
|
[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) ->
|
|
[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) ->
|
|
[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) ->
|
|
[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) ->
|
|
[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) ->
|
|
[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) ->
|
|
[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) ->
|
|
[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) ->
|
|
[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) ->
|
|
[ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) ->
|
|
[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) ->
|
|
[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) ->
|
|
[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) ->
|
|
[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) ->
|
|
[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) ->
|
|
[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) ->
|
|
[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) ->
|
|
[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) ->
|
|
[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) ->
|
|
[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) ->
|
|
[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) ->
|
|
[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) ->
|
|
[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) ->
|
|
[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) ->
|
|
[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) ->
|
|
[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) ->
|
|
[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) ->
|
|
[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) ->
|
|
[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) ->
|
|
[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) ->
|
|
[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) ->
|
|
[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) ->
|
|
[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) ->
|
|
[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) ->
|
|
[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) ->
|
|
[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) ->
|
|
[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) ->
|
|
[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) ->
|
|
[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) ->
|
|
[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) ->
|
|
[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) ->
|
|
[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) ->
|
|
[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) ->
|
|
[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) ->
|
|
[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) ->
|
|
[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) ->
|
|
[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) ->
|
|
[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) ->
|
|
[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) ->
|
|
[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) ->
|
|
[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) ->
|
|
[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) ->
|
|
[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) ->
|
|
[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) ->
|
|
[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) ->
|
|
[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) ->
|
|
[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) ->
|
|
[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) ->
|
|
[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) ->
|
|
[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) ->
|
|
[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) ->
|
|
[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) ->
|
|
[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) ->
|
|
[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) ->
|
|
[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) ->
|
|
[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) ->
|
|
[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) ->
|
|
[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) ->
|
|
[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) ->
|
|
[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) ->
|
|
[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) ->
|
|
[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) ->
|
|
[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) ->
|
|
[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) ->
|
|
[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) ->
|
|
[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) ->
|
|
[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) ->
|
|
[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) ->
|
|
[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) ->
|
|
[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) ->
|
|
[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) ->
|
|
[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) ->
|
|
[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) ->
|
|
[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) ->
|
|
[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) ->
|
|
[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) ->
|
|
[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) ->
|
|
[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) ->
|
|
[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) ->
|
|
[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) ->
|
|
[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) ->
|
|
[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 152) ->
|
|
[10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [145000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[27500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [20000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) ->
|
|
[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) ->
|
|
[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) ->
|
|
[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) ->
|
|
[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) ->
|
|
[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) ->
|
|
[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) ->
|
|
[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) ->
|
|
[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) ->
|
|
[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) ->
|
|
[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) ->
|
|
[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) ->
|
|
[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) ->
|
|
[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) ->
|
|
[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) ->
|
|
[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) ->
|
|
[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) ->
|
|
[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) ->
|
|
[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) ->
|
|
[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) ->
|
|
[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) ->
|
|
[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) ->
|
|
[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) ->
|
|
[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) ->
|
|
[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) ->
|
|
[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) ->
|
|
[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) ->
|
|
[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) ->
|
|
[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) ->
|
|
[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) ->
|
|
[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) ->
|
|
[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) ->
|
|
[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) ->
|
|
[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) ->
|
|
[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) ->
|
|
[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) ->
|
|
[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) ->
|
|
[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) ->
|
|
[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) ->
|
|
[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) ->
|
|
[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) ->
|
|
[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) ->
|
|
[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) ->
|
|
[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) ->
|
|
[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) ->
|
|
[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) ->
|
|
[ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) ->
|
|
[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
|
|
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
|
|
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
|
|
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
|
|
[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
|
|
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
|
|
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
|
|
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
|
|
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
|
|
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
|
|
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
|
|
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
|
|
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
|
|
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
|
|
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
|
|
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
|
|
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
|
|
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
|
|
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
|
|
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
|
|
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
|
|
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
|
|
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
|
|
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) ->
|
|
[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) ->
|
|
[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) ->
|
|
[20000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) ->
|
|
[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) ->
|
|
[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) ->
|
|
[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) ->
|
|
[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) ->
|
|
[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) ->
|
|
[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) ->
|
|
[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) ->
|
|
[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) ->
|
|
[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) ->
|
|
[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) ->
|
|
[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) ->
|
|
[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) ->
|
|
[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) ->
|
|
[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) ->
|
|
[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) ->
|
|
[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) ->
|
|
[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) ->
|
|
[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) ->
|
|
[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) ->
|
|
[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) ->
|
|
[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) ->
|
|
[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) ->
|
|
[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) ->
|
|
[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) ->
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) ->
|
|
[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) ->
|
|
[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) ->
|
|
[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) ->
|
|
[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) ->
|
|
[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) ->
|
|
[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) ->
|
|
[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) ->
|
|
[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) ->
|
|
[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) ->
|
|
[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) ->
|
|
[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) ->
|
|
[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) ->
|
|
[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) ->
|
|
[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) ->
|
|
[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) ->
|
|
[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) ->
|
|
[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) ->
|
|
[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) ->
|
|
[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) ->
|
|
[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) ->
|
|
[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) ->
|
|
[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) ->
|
|
[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) ->
|
|
[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) ->
|
|
[ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) ->
|
|
[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) ->
|
|
[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) ->
|
|
[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) ->
|
|
[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) ->
|
|
[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) ->
|
|
[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) ->
|
|
[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) ->
|
|
[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) ->
|
|
[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) ->
|
|
[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) ->
|
|
[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) ->
|
|
[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) ->
|
|
[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) ->
|
|
[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) ->
|
|
[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) ->
|
|
[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) ->
|
|
[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) ->
|
|
[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) ->
|
|
[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) ->
|
|
[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) ->
|
|
[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) ->
|
|
[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) ->
|
|
[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) ->
|
|
[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) ->
|
|
[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) ->
|
|
[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) ->
|
|
[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) ->
|
|
[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) ->
|
|
[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) ->
|
|
[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) ->
|
|
[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 176) ->
|
|
[10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [147500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[27500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [20000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) ->
|
|
[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) ->
|
|
[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) ->
|
|
[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) ->
|
|
[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) ->
|
|
[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) ->
|
|
[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) ->
|
|
[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) ->
|
|
[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) ->
|
|
[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) ->
|
|
[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) ->
|
|
[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) ->
|
|
[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) ->
|
|
[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) ->
|
|
[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) ->
|
|
[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) ->
|
|
[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) ->
|
|
[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) ->
|
|
[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) ->
|
|
[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) ->
|
|
[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) ->
|
|
[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) ->
|
|
[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) ->
|
|
[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) ->
|
|
[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) ->
|
|
[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) ->
|
|
[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) ->
|
|
[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) ->
|
|
[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) ->
|
|
[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) ->
|
|
[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) ->
|
|
[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) ->
|
|
[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) ->
|
|
[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) ->
|
|
[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) ->
|
|
[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) ->
|
|
[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) ->
|
|
[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) ->
|
|
[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) ->
|
|
[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) ->
|
|
[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) ->
|
|
[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) ->
|
|
[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) ->
|
|
[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) ->
|
|
[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) ->
|
|
[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) ->
|
|
[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) ->
|
|
[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) ->
|
|
[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) ->
|
|
[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) ->
|
|
[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) ->
|
|
[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) ->
|
|
[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) ->
|
|
[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) ->
|
|
[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) ->
|
|
[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) ->
|
|
[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) ->
|
|
[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) ->
|
|
[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) ->
|
|
[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) ->
|
|
[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) ->
|
|
[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) ->
|
|
[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) ->
|
|
[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) ->
|
|
[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) ->
|
|
[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) ->
|
|
[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) ->
|
|
[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) ->
|
|
[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) ->
|
|
[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) ->
|
|
[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) ->
|
|
[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) ->
|
|
[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) ->
|
|
[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) ->
|
|
[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) ->
|
|
[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) ->
|
|
[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) ->
|
|
[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) ->
|
|
[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) ->
|
|
[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) ->
|
|
[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) ->
|
|
[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) ->
|
|
[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) ->
|
|
[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) ->
|
|
[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) ->
|
|
[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) ->
|
|
[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) ->
|
|
[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) ->
|
|
[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) ->
|
|
[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) ->
|
|
[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) ->
|
|
[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) ->
|
|
[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) ->
|
|
[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) ->
|
|
[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) ->
|
|
[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) ->
|
|
[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) ->
|
|
[ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) ->
|
|
[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) ->
|
|
[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) ->
|
|
[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) ->
|
|
[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) ->
|
|
[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) ->
|
|
[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) ->
|
|
[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) ->
|
|
[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) ->
|
|
[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) ->
|
|
[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) ->
|
|
[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) ->
|
|
[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) ->
|
|
[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) ->
|
|
[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) ->
|
|
[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) ->
|
|
[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) ->
|
|
[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) ->
|
|
[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) ->
|
|
[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) ->
|
|
[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) ->
|
|
[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) ->
|
|
[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) ->
|
|
[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) ->
|
|
[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) ->
|
|
[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) ->
|
|
[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) ->
|
|
[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
|
|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
|
|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) -> [10000 ps] RD @ (0, 992) ->
|
|
DONE TEST 1: LAST ROW
|
|
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) ->
|
|
[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) ->
|
|
[10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) ->
|
|
[17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) ->
|
|
[25000 ps] NOP -> [20000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [115000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 12761) -> [17500 ps] WR @ (0, 952) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11682) -> [17500 ps] WR @ (0, 952) -> [12500 ps] ACT @ (4, 10602) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 5206) -> [10000 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [17500 ps] WR @ (0, 944) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 890) ->
|
|
[17500 ps] WR @ (0, 944) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16194) -> [17500 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [17500 ps] WR @ (0, 928) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6482) ->
|
|
[17500 ps] WR @ (0, 928) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5402) -> [17500 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) ->
|
|
[17500 ps] WR @ (0, 920) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [17500 ps] WR @ (4, 920) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8836) -> [17500 ps] WR @ (0, 920) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) ->
|
|
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) ->
|
|
[17500 ps] WR @ (0, 912) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [17500 ps] WR @ (4, 912) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14428) -> [17500 ps] WR @ (0, 904) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) ->
|
|
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) ->
|
|
[17500 ps] WR @ (0, 896) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [17500 ps] WR @ (4, 896) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3636) -> [17500 ps] WR @ (0, 896) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) ->
|
|
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [17500 ps] WR @ (0, 888) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7069) ->
|
|
[17500 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [25000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) ->
|
|
[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [17500 ps] WR @ (0, 872) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12661) ->
|
|
[17500 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [25000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [17500 ps] WR @ (0, 864) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1869) ->
|
|
[17500 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [25000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) ->
|
|
[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) ->
|
|
[17500 ps] WR @ (4, 848) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5303) -> [17500 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) ->
|
|
[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) ->
|
|
[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) ->
|
|
[17500 ps] WR @ (4, 840) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 10895) -> [17500 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) ->
|
|
[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) ->
|
|
[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) ->
|
|
[17500 ps] WR @ (4, 832) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 103) -> [17500 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) ->
|
|
[10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) ->
|
|
[17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) ->
|
|
[10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) ->
|
|
[17500 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5695) -> [17500 ps] WR @ (0, 816) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3536) -> [17500 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) ->
|
|
[17500 ps] WR @ (4, 816) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) ->
|
|
[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [105000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[27500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> [ 7500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [17500 ps] WR @ (0, 808) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10208) ->
|
|
[17500 ps] WR @ (0, 808) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9128) -> [17500 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [17500 ps] WR @ (0, 800) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15800) ->
|
|
[17500 ps] WR @ (0, 792) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14720) -> [17500 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 9324) -> [10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) ->
|
|
[17500 ps] WR @ (0, 784) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [17500 ps] WR @ (4, 784) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1770) -> [17500 ps] WR @ (0, 784) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) ->
|
|
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) ->
|
|
[17500 ps] WR @ (0, 776) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [17500 ps] WR @ (4, 776) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7362) -> [17500 ps] WR @ (0, 768) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) ->
|
|
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) ->
|
|
[17500 ps] WR @ (0, 760) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [17500 ps] WR @ (4, 760) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12954) -> [17500 ps] WR @ (0, 760) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) ->
|
|
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [17500 ps] WR @ (0, 752) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3) ->
|
|
[17500 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [25000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) ->
|
|
[10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [17500 ps] WR @ (0, 736) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5595) ->
|
|
[17500 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [25000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) ->
|
|
[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [17500 ps] WR @ (0, 728) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11187) ->
|
|
[17500 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [25000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) ->
|
|
[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) ->
|
|
[17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) ->
|
|
[17500 ps] WR @ (4, 720) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 14621) -> [17500 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) ->
|
|
[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) ->
|
|
[17500 ps] WR @ (4, 704) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 3829) -> [17500 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) ->
|
|
[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) ->
|
|
[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) ->
|
|
[17500 ps] WR @ (4, 696) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9421) -> [17500 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) ->
|
|
[10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) ->
|
|
[17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) ->
|
|
[10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) ->
|
|
[17500 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 15013) -> [17500 ps] WR @ (0, 680) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12854) -> [17500 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) ->
|
|
[17500 ps] WR @ (4, 680) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) ->
|
|
[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) ->
|
|
[10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) ->
|
|
[17500 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 4221) -> [ 2500 ps] NOP -> [15000 ps] WR @ (0, 672) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3142) ->
|
|
[17500 ps] WR @ (0, 672) -> [75000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2062) ->
|
|
[17500 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [22500 ps] ACT @ (0, 15209) ->
|
|
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) ->
|
|
[17500 ps] WR @ (4, 664) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [17500 ps] WR @ (0, 664) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7654) -> [17500 ps] WR @ (4, 656) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) ->
|
|
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) ->
|
|
[10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [17500 ps] WR @ (4, 648) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11088) ->
|
|
[17500 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) ->
|
|
[10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [17500 ps] WR @ (4, 640) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 296) ->
|
|
[17500 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) ->
|
|
[10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [17500 ps] WR @ (4, 624) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5888) ->
|
|
[17500 ps] WR @ (0, 624) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 2650) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) ->
|
|
[10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) ->
|
|
[17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) ->
|
|
[17500 ps] WR @ (0, 616) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9321) -> [17500 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) ->
|
|
[10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) ->
|
|
[17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) ->
|
|
[17500 ps] WR @ (0, 608) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14913) -> [17500 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) ->
|
|
[10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) ->
|
|
[17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) ->
|
|
[17500 ps] WR @ (0, 592) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4121) -> [17500 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) ->
|
|
[10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) ->
|
|
[17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) ->
|
|
[10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) ->
|
|
[17500 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9713) -> [17500 ps] WR @ (4, 584) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7555) -> [17500 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) ->
|
|
[17500 ps] WR @ (0, 576) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) ->
|
|
[17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) ->
|
|
[10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) ->
|
|
[17500 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15305) -> [17500 ps] WR @ (4, 568) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13147) -> [17500 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) ->
|
|
[17500 ps] WR @ (0, 568) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) ->
|
|
[17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) ->
|
|
[10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) ->
|
|
[17500 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4513) -> [17500 ps] WR @ (4, 560) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2355) -> [17500 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) ->
|
|
[17500 ps] WR @ (0, 560) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) ->
|
|
[17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) ->
|
|
[10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [17500 ps] WR @ (0, 544) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6868) ->
|
|
[17500 ps] WR @ (0, 544) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5788) -> [17500 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [17500 ps] WR @ (0, 536) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12460) ->
|
|
[17500 ps] WR @ (0, 536) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11380) -> [17500 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [125000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [12500 ps] ACT @ (0, 2747) -> [17500 ps] WR @ (0, 528) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 588) -> [17500 ps] WR @ (4, 528) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) ->
|
|
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) ->
|
|
[10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [17500 ps] WR @ (4, 512) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4022) ->
|
|
[17500 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) ->
|
|
[10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [17500 ps] WR @ (4, 504) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9614) ->
|
|
[17500 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) ->
|
|
[10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [17500 ps] WR @ (4, 496) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15206) ->
|
|
[17500 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) ->
|
|
[10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) ->
|
|
[17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) ->
|
|
[17500 ps] WR @ (0, 480) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 2255) -> [17500 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) ->
|
|
[10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) ->
|
|
[17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) ->
|
|
[17500 ps] WR @ (0, 472) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 7847) -> [17500 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) ->
|
|
[10000 ps] WR @ (0, 464) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2451) -> [10000 ps] ACT @ (0, 3531) ->
|
|
[17500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) ->
|
|
[17500 ps] WR @ (0, 456) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 13439) -> [17500 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) ->
|
|
[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) ->
|
|
[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) ->
|
|
[10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) ->
|
|
[17500 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 2647) -> [17500 ps] WR @ (4, 448) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 489) -> [17500 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) ->
|
|
[17500 ps] WR @ (0, 440) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) ->
|
|
[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) ->
|
|
[10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) ->
|
|
[17500 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8239) -> [17500 ps] WR @ (4, 440) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6081) -> [17500 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) ->
|
|
[17500 ps] WR @ (0, 432) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) ->
|
|
[17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) ->
|
|
[10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) ->
|
|
[17500 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 13831) -> [17500 ps] WR @ (4, 424) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11673) -> [17500 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) ->
|
|
[17500 ps] WR @ (0, 424) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) ->
|
|
[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) ->
|
|
[10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [17500 ps] WR @ (0, 416) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16186) ->
|
|
[17500 ps] WR @ (0, 408) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15106) -> [17500 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [17500 ps] WR @ (0, 400) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5394) ->
|
|
[17500 ps] WR @ (0, 400) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4314) -> [17500 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [17500 ps] WR @ (0, 392) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10986) ->
|
|
[17500 ps] WR @ (0, 392) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9906) -> [17500 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [55000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[27500 ps] ACT @ (4, 7748) -> [10000 ps] ACT @ (0, 6669) -> [ 7500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) ->
|
|
[10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [17500 ps] WR @ (4, 376) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13340) ->
|
|
[17500 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) ->
|
|
[10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [17500 ps] WR @ (4, 368) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2548) ->
|
|
[17500 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) ->
|
|
[10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [17500 ps] WR @ (4, 360) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8140) ->
|
|
[17500 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) ->
|
|
[10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) ->
|
|
[17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) ->
|
|
[17500 ps] WR @ (0, 344) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 11573) -> [17500 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) ->
|
|
[10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) ->
|
|
[17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) ->
|
|
[17500 ps] WR @ (0, 336) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 781) -> [17500 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) ->
|
|
[10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) ->
|
|
[17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) ->
|
|
[17500 ps] WR @ (0, 328) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 6373) -> [17500 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) ->
|
|
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) ->
|
|
[10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) ->
|
|
[17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) ->
|
|
[10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) ->
|
|
[17500 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 11965) -> [17500 ps] WR @ (4, 312) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9807) -> [17500 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) ->
|
|
[17500 ps] WR @ (0, 312) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) ->
|
|
[17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) ->
|
|
[10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) ->
|
|
[17500 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15399) -> [17500 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) ->
|
|
[17500 ps] WR @ (0, 296) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) ->
|
|
[17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) ->
|
|
[10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) ->
|
|
[17500 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [15000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 6765) -> [17500 ps] WR @ (4, 288) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4607) -> [17500 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) ->
|
|
[17500 ps] WR @ (0, 288) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) ->
|
|
[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) ->
|
|
[10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [17500 ps] WR @ (0, 280) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9120) ->
|
|
[17500 ps] WR @ (0, 280) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8040) -> [17500 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [17500 ps] WR @ (0, 264) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14712) ->
|
|
[17500 ps] WR @ (0, 264) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13632) -> [17500 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) ->
|
|
[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [17500 ps] WR @ (0, 256) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3920) ->
|
|
[17500 ps] WR @ (0, 256) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2840) -> [17500 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) ->
|
|
[15000 ps] NOP -> [30000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [25000 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 183175100.0 ps ERROR: tWR violation during Precharge to bank 0
|
|
[30000 ps] REF -> [360000 ps] NOP ->
|
|
[17500 ps] ACT @ (4, 8432) -> [17500 ps] WR @ (4, 248) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) ->
|
|
[12500 ps] ACT @ (0, 6274) -> [17500 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) ->
|
|
[10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) ->
|
|
[17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) ->
|
|
[17500 ps] WR @ (4, 232) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11866) -> [17500 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) ->
|
|
[17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) ->
|
|
[17500 ps] WR @ (4, 224) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 1074) -> [17500 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) ->
|
|
[10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) ->
|
|
[17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) ->
|
|
[10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) ->
|
|
[17500 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 6666) -> [17500 ps] WR @ (0, 208) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4507) -> [17500 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) ->
|
|
[17500 ps] WR @ (4, 208) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) ->
|
|
[17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) ->
|
|
[10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) ->
|
|
[17500 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 12258) -> [17500 ps] WR @ (0, 200) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10099) -> [17500 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) ->
|
|
[17500 ps] WR @ (4, 200) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) ->
|
|
[17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) ->
|
|
[10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) ->
|
|
[17500 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 1466) -> [17500 ps] WR @ (0, 192) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15691) -> [17500 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) ->
|
|
[17500 ps] WR @ (4, 184) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) ->
|
|
[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) ->
|
|
[10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [17500 ps] WR @ (4, 176) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3820) ->
|
|
[17500 ps] WR @ (4, 176) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2741) -> [17500 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [17500 ps] WR @ (4, 168) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9412) ->
|
|
[17500 ps] WR @ (4, 168) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8333) -> [17500 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [17500 ps] WR @ (4, 152) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15004) ->
|
|
[17500 ps] WR @ (4, 152) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13925) -> [17500 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [17500 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) ->
|
|
[17500 ps] WR @ (4, 144) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [17500 ps] WR @ (0, 144) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 974) -> [17500 ps] WR @ (4, 144) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) ->
|
|
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) ->
|
|
[17500 ps] WR @ (4, 136) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [17500 ps] WR @ (0, 136) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6566) -> [17500 ps] WR @ (4, 128) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) ->
|
|
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) ->
|
|
[17500 ps] WR @ (4, 120) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [17500 ps] WR @ (0, 120) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12158) -> [17500 ps] WR @ (4, 120) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) ->
|
|
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) ->
|
|
[10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [17500 ps] WR @ (4, 112) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15592) ->
|
|
[17500 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [25000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) ->
|
|
[105000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) ->
|
|
[ 7500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) ->
|
|
[17500 ps] WR @ (4, 96) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 4800) -> [17500 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) ->
|
|
[10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) ->
|
|
[17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) ->
|
|
[17500 ps] WR @ (4, 88) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 10392) -> [17500 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) ->
|
|
[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) ->
|
|
[10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) ->
|
|
[17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) ->
|
|
[10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) ->
|
|
[17500 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 15984) -> [17500 ps] WR @ (0, 72) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13825) -> [17500 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) ->
|
|
[17500 ps] WR @ (4, 72) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) ->
|
|
[17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) ->
|
|
[10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) ->
|
|
[17500 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5192) -> [17500 ps] WR @ (0, 64) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3033) -> [17500 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) ->
|
|
[17500 ps] WR @ (4, 64) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) ->
|
|
[17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) ->
|
|
[10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) ->
|
|
[17500 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [15000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 10784) -> [17500 ps] WR @ (0, 56) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8625) -> [17500 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) ->
|
|
[17500 ps] WR @ (4, 48) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) ->
|
|
[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) ->
|
|
[10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [17500 ps] WR @ (4, 40) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13138) ->
|
|
[17500 ps] WR @ (4, 40) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12059) -> [17500 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [ 2500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [17500 ps] WR @ (4, 32) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2346) ->
|
|
[17500 ps] WR @ (4, 32) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1267) -> [17500 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [ 2500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) ->
|
|
[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [17500 ps] WR @ (4, 24) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7938) ->
|
|
[17500 ps] WR @ (4, 16) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6859) -> [17500 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [ 2500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) ->
|
|
[17500 ps] WR @ (4, 8) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [17500 ps] WR @ (0, 8) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10292) -> [17500 ps] WR @ (4, 8) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) ->
|
|
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) ->
|
|
[17500 ps] WR @ (4, 0) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [17500 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> [22500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [15000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [17500 ps] WR @ (3, 1016) ->
|
|
[15000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) ->
|
|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10488) -> [17500 ps] WR @ (7, 1016) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8331) ->
|
|
[12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) ->
|
|
[17500 ps] WR @ (7, 1016) -> [12500 ps] ACT @ (4, 7251) -> [12500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 198485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[ 7500 ps] ACT @ (3, 7251) ->
|
|
[10000 ps] ACT @ (4, 6172) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 198502600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
[ 7500 ps] WR @ (3, 1008) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) ->
|
|
[15000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 4014) -> [10000 ps] ACT @ (7, 5092) -> [17500 ps] WR @ (7, 1008) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) -> [15000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> [15000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16081) -> [22500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 776) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) ->
|
|
[15000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) ->
|
|
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13922) -> [17500 ps] WR @ (3, 1000) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11764) ->
|
|
[12500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) ->
|
|
[17500 ps] WR @ (3, 1000) -> [12500 ps] ACT @ (0, 10685) -> [12500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 199285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[ 7500 ps] ACT @ (7, 10684) ->
|
|
[10000 ps] ACT @ (0, 9606) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 199302600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
[ 7500 ps] WR @ (7, 1000) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) ->
|
|
[15000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 7447) -> [10000 ps] ACT @ (3, 8526) -> [17500 ps] WR @ (3, 1000) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [15000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 5288) -> [17500 ps] WR @ (7, 992) -> [15000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (3, 3130) ->
|
|
[17500 ps] WR @ (3, 992) -> [145000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2051) ->
|
|
[10000 ps] ACT @ (3, 2051) -> [ 2500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 200335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[15000 ps] WR @ (3, 992) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) ->
|
|
[17500 ps] WR @ (3, 992) -> [12500 ps] ACT @ (0, 16277) -> [10000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 200455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[15000 ps] WR @ (7, 984) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [12500 ps] ACT @ (4, 14118) -> [12500 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 200585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 200602600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
[ 7500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [15000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10880) -> [17500 ps] WR @ (7, 984) ->
|
|
[15000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) ->
|
|
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) ->
|
|
[17500 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [15000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 5484) -> [17500 ps] WR @ (7, 976) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) ->
|
|
[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3326) -> [17500 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) ->
|
|
[17500 ps] WR @ (3, 976) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) ->
|
|
[17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) ->
|
|
[10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
|
|
[ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> [10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) ->
|
|
[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [17500 ps] WR @ (3, 968) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7839) ->
|
|
[17500 ps] WR @ (3, 960) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6759) -> [17500 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
|
|
[ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) ->
|
|
[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [17500 ps] WR @ (3, 952) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13431) ->
|
|
[17500 ps] WR @ (3, 952) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12351) -> [17500 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
|
|
[ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) ->
|
|
[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [17500 ps] WR @ (3, 944) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2639) ->
|
|
[17500 ps] WR @ (3, 944) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1559) -> [17500 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
|
|
[ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) ->
|
|
[17500 ps] WR @ (3, 936) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [17500 ps] WR @ (7, 928) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 6072) -> [17500 ps] WR @ (7, 928) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4993) -> [17500 ps] WR @ (3, 928) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) ->
|
|
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) ->
|
|
[17500 ps] WR @ (3, 920) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [17500 ps] WR @ (7, 920) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 11664) -> [17500 ps] WR @ (7, 920) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10585) -> [17500 ps] WR @ (3, 920) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) ->
|
|
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) ->
|
|
[17500 ps] WR @ (3, 912) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [17500 ps] WR @ (7, 912) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 872) -> [17500 ps] WR @ (7, 912) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16177) -> [17500 ps] WR @ (3, 904) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) ->
|
|
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> [17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) ->
|
|
[10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [17500 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 6464) -> [17500 ps] WR @ (7, 896) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [17500 ps] WR @ (3, 896) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3226) ->
|
|
[17500 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [17500 ps] WR @ (7, 896) -> [25000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> [10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) ->
|
|
[10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [17500 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 12056) -> [17500 ps] WR @ (7, 888) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [17500 ps] WR @ (3, 888) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8818) ->
|
|
[17500 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [17500 ps] WR @ (7, 880) -> [25000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> [10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) ->
|
|
[10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [17500 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 1264) -> [17500 ps] WR @ (7, 880) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [17500 ps] WR @ (3, 880) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14410) ->
|
|
[17500 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [17500 ps] WR @ (7, 872) -> [25000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> [10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) ->
|
|
[10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) ->
|
|
[17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) ->
|
|
[17500 ps] WR @ (7, 864) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [15000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 1460) -> [17500 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) ->
|
|
[25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) ->
|
|
[10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) ->
|
|
[17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) ->
|
|
[17500 ps] WR @ (7, 856) -> [15000 ps] NOP -> [30000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) ->
|
|
[105000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 7052) -> [17500 ps] WR @ (3, 848) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [22500 ps] ACT @ (7, 3814) -> [22500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [10000 ps] WR @ (7, 848) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 1656) -> [10000 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) ->
|
|
[15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [17500 ps] WR @ (7, 840) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13723) ->
|
|
[17500 ps] WR @ (7, 840) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12644) -> [17500 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) ->
|
|
[17500 ps] WR @ (7, 832) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [17500 ps] WR @ (3, 832) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 773) -> [17500 ps] WR @ (3, 832) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16077) -> [17500 ps] WR @ (7, 824) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> [17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) ->
|
|
[17500 ps] WR @ (7, 824) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [17500 ps] WR @ (3, 816) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 6365) -> [17500 ps] WR @ (3, 816) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5285) -> [17500 ps] WR @ (7, 816) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) ->
|
|
[17500 ps] WR @ (7, 808) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [17500 ps] WR @ (3, 808) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 11957) -> [17500 ps] WR @ (3, 808) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10877) -> [17500 ps] WR @ (7, 808) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) ->
|
|
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) ->
|
|
[10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [17500 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 1165) -> [17500 ps] WR @ (3, 800) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [17500 ps] WR @ (7, 800) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14311) ->
|
|
[17500 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [17500 ps] WR @ (3, 792) -> [25000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) ->
|
|
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> [10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) ->
|
|
[10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [17500 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 6757) -> [17500 ps] WR @ (3, 784) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [17500 ps] WR @ (7, 784) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3519) ->
|
|
[17500 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [17500 ps] WR @ (3, 784) -> [25000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) ->
|
|
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> [10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) ->
|
|
[10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [17500 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 12349) -> [17500 ps] WR @ (3, 776) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [17500 ps] WR @ (7, 776) ->
|
|
[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9111) ->
|
|
[17500 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> [17500 ps] WR @ (3, 768) -> [25000 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [17500 ps] WR @ (3, 768) -> [10000 ps] WR @ (7, 768) ->
|
|
[ 2500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [25000 ps] RD @ (4, 960) -> [10000 ps] RD @ (0, 960) -> [17500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 694) -> [10000 ps] ACT @ (4, 15998) -> [ 5000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 213445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 13840) ->
|
|
[15000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [15000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 213545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 11682) -> [15000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10602) -> [15000 ps] RD @ (4, 952) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 213645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 8444) -> [10000 ps] ACT @ (0, 7365) -> [ 5000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 944) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 213895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3048) ->
|
|
[15000 ps] RD @ (4, 944) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [15000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 213995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 890) -> [15000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16194) -> [15000 ps] RD @ (4, 936) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 214095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 14036) -> [10000 ps] ACT @ (0, 12957) -> [ 5000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 936) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> [ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 214345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 8640) ->
|
|
[15000 ps] RD @ (4, 936) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [15000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 214445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 6482) -> [15000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5402) -> [15000 ps] RD @ (4, 928) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 214545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 3244) -> [10000 ps] ACT @ (0, 2165) -> [ 5000 ps] RD @ (4, 928) -> [10000 ps] RD @ (0, 928) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15311) -> [10000 ps] ACT @ (0, 14232) -> [ 5000 ps] RD @ (4, 920) ->
|
|
[10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [15000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 214865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12074) -> [15000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [15000 ps] RD @ (4, 920) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 214965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9915) -> [15000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8836) ->
|
|
[15000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 215065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7757) -> [15000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6678) -> [10000 ps] ACT @ (4, 5598) -> [ 5000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> [10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) ->
|
|
[10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [15000 ps] RD @ (0, 912) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 215315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1282) -> [15000 ps] RD @ (0, 912) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [15000 ps] RD @ (4, 912) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 215415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15507) -> [15000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14428) ->
|
|
[15000 ps] RD @ (0, 904) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 215515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 13349) -> [15000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12270) -> [10000 ps] ACT @ (4, 11190) -> [ 5000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> [10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) ->
|
|
[10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [15000 ps] RD @ (0, 896) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 215765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 6874) -> [15000 ps] RD @ (0, 896) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [15000 ps] RD @ (4, 896) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 215865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 4715) -> [15000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3636) ->
|
|
[15000 ps] RD @ (0, 896) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 215965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2557) -> [15000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1478) -> [10000 ps] ACT @ (4, 398) -> [ 5000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> [10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) ->
|
|
[10000 ps] RD @ (0, 888) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13545) -> [10000 ps] ACT @ (4, 12465) ->
|
|
[ 5000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 216285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) ->
|
|
[15000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 216385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8149) -> [15000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 7069) -> [15000 ps] RD @ (4, 880) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 216485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) ->
|
|
[137500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (4, 4911) -> [10000 ps] ACT @ (0, 3832) ->
|
|
[ 5000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2753) ->
|
|
[10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) ->
|
|
[15000 ps] RD @ (4, 880) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 217245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 14820) -> [15000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 217345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 13741) -> [15000 ps] RD @ (0, 872) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12661) -> [15000 ps] RD @ (4, 872) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 217445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11582) ->
|
|
[15000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10503) -> [10000 ps] ACT @ (0, 9424) ->
|
|
[ 5000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8345) ->
|
|
[10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) ->
|
|
[15000 ps] RD @ (4, 864) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 217695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 4028) -> [15000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 217795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2949) -> [15000 ps] RD @ (0, 864) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1869) -> [15000 ps] RD @ (4, 864) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 217895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 790) ->
|
|
[15000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16095) -> [10000 ps] ACT @ (0, 15016) ->
|
|
[ 5000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13937) ->
|
|
[10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 11778) -> [10000 ps] ACT @ (0, 10699) -> [ 5000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 218215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [15000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 218315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6382) ->
|
|
[15000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5303) -> [15000 ps] RD @ (0, 848) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 218415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3145) ->
|
|
[10000 ps] ACT @ (4, 2065) -> [ 5000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 218665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [15000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 218765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11974) ->
|
|
[15000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10895) -> [15000 ps] RD @ (0, 840) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 218865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8737) ->
|
|
[10000 ps] ACT @ (4, 7657) -> [ 5000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 219115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [15000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 219215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1182) ->
|
|
[15000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 103) -> [15000 ps] RD @ (0, 832) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 219315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14329) ->
|
|
[10000 ps] ACT @ (4, 13249) -> [ 5000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10012) -> [10000 ps] ACT @ (4, 8932) -> [ 5000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 219635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6774) ->
|
|
[15000 ps] RD @ (4, 816) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [15000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 219735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 4616) -> [15000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3536) -> [15000 ps] RD @ (4, 816) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 219835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 1378) -> [10000 ps] ACT @ (0, 299) -> [ 5000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 220085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12366) ->
|
|
[15000 ps] RD @ (4, 808) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [15000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 220185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10208) -> [15000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9128) -> [15000 ps] RD @ (4, 808) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 220285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6970) -> [10000 ps] ACT @ (0, 5891) -> [ 5000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 220535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1574) ->
|
|
[15000 ps] RD @ (4, 800) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [15000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 220635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 15800) -> [15000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14720) -> [15000 ps] RD @ (4, 792) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 220735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 12562) -> [10000 ps] ACT @ (0, 11483) -> [ 5000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8245) -> [10000 ps] ACT @ (0, 7166) -> [ 5000 ps] RD @ (4, 792) ->
|
|
[10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 221055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [15000 ps] RD @ (4, 784) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 221155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 2849) -> [15000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1770) ->
|
|
[15000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 221255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15996) -> [10000 ps] ACT @ (4, 14916) -> [ 5000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) ->
|
|
[10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 221505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [15000 ps] RD @ (4, 776) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 221605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 8441) -> [15000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7362) ->
|
|
[15000 ps] RD @ (0, 768) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 221705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5204) -> [10000 ps] ACT @ (4, 4124) -> [ 5000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) ->
|
|
[10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 221955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [15000 ps] RD @ (4, 760) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 222055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14033) -> [15000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12954) ->
|
|
[15000 ps] RD @ (0, 760) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 222155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10796) -> [10000 ps] ACT @ (4, 9716) -> [ 5000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) ->
|
|
[10000 ps] RD @ (0, 752) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6479) -> [10000 ps] ACT @ (4, 5399) ->
|
|
[ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 222475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) ->
|
|
[15000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 222575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1083) -> [15000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3) -> [15000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 222675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14229) -> [10000 ps] ACT @ (0, 13150) -> [ 5000 ps] RD @ (4, 744) ->
|
|
[10000 ps] RD @ (0, 744) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) ->
|
|
[ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 222925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) ->
|
|
[15000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 223025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 6675) -> [15000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 5595) -> [15000 ps] RD @ (4, 736) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 223125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3437) -> [10000 ps] ACT @ (0, 2358) -> [ 5000 ps] RD @ (4, 736) ->
|
|
[10000 ps] RD @ (0, 736) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) ->
|
|
[ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 223375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) ->
|
|
[15000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 223475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12267) -> [15000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 11187) -> [15000 ps] RD @ (4, 728) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 223575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9029) -> [10000 ps] ACT @ (0, 7950) -> [ 5000 ps] RD @ (4, 728) ->
|
|
[10000 ps] RD @ (0, 720) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) ->
|
|
[ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4712) ->
|
|
[10000 ps] ACT @ (0, 3633) -> [ 5000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) ->
|
|
[15000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 223895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 395) -> [15000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 223995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15700) -> [15000 ps] RD @ (4, 712) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14621) -> [15000 ps] RD @ (0, 712) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 224095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 13542) ->
|
|
[15000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12463) -> [10000 ps] ACT @ (4, 11383) ->
|
|
[ 5000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) ->
|
|
[10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) ->
|
|
[15000 ps] RD @ (0, 704) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 224345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 5987) -> [15000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 224445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 4908) -> [15000 ps] RD @ (4, 704) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3829) -> [15000 ps] RD @ (0, 704) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 224545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2750) ->
|
|
[15000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1671) -> [10000 ps] ACT @ (4, 591) ->
|
|
[ 5000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) ->
|
|
[10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) ->
|
|
[15000 ps] RD @ (0, 696) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 224795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [17500 ps] PRE @ (4) ->
|
|
[10000 ps] NOP -> [ 7500 ps] ACT @ (4, 11579) -> [15000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 224895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10500) ->
|
|
[15000 ps] RD @ (4, 696) -> [97500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9421) ->
|
|
[15000 ps] RD @ (0, 696) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 225465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [25000 ps] ACT @ (4, 6183) ->
|
|
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2946) -> [10000 ps] ACT @ (4, 1866) -> [ 5000 ps] RD @ (0, 688) ->
|
|
[10000 ps] RD @ (4, 688) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 225775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [15000 ps] RD @ (0, 680) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 225875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 13934) -> [15000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12854) ->
|
|
[15000 ps] RD @ (4, 680) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 225975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10696) -> [10000 ps] ACT @ (0, 9617) -> [ 5000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) ->
|
|
[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 226225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [15000 ps] RD @ (0, 672) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 226325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3142) -> [15000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2062) ->
|
|
[15000 ps] RD @ (4, 672) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 226425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16288) -> [10000 ps] ACT @ (0, 15209) -> [ 5000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 226675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [15000 ps] RD @ (0, 664) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 226775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8734) -> [15000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7654) ->
|
|
[15000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 226875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5496) -> [10000 ps] ACT @ (0, 4417) -> [ 5000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) ->
|
|
[10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1179) -> [10000 ps] ACT @ (0, 100) ->
|
|
[ 5000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 227195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) ->
|
|
[15000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 227295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12167) -> [15000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11088) -> [15000 ps] RD @ (0, 648) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 227395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8930) -> [10000 ps] ACT @ (4, 7850) -> [ 5000 ps] RD @ (0, 648) ->
|
|
[10000 ps] RD @ (4, 640) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) ->
|
|
[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 227645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) ->
|
|
[15000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 227745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1375) -> [15000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 296) -> [15000 ps] RD @ (0, 640) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 227845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14522) -> [10000 ps] ACT @ (4, 13442) -> [ 5000 ps] RD @ (0, 632) ->
|
|
[10000 ps] RD @ (4, 632) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) ->
|
|
[ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 228095100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) ->
|
|
[15000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 228195100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6967) -> [15000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 5888) -> [15000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 228295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3730) -> [10000 ps] ACT @ (4, 2650) -> [ 5000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (4, 624) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1571) -> [10000 ps] ACT @ (0, 492) ->
|
|
[ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) ->
|
|
[10000 ps] ACT @ (4, 14717) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) ->
|
|
[15000 ps] RD @ (4, 616) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 228615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11480) -> [15000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 228715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10401) -> [15000 ps] RD @ (0, 616) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9321) -> [15000 ps] RD @ (4, 616) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 228815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 8242) ->
|
|
[15000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7163) -> [10000 ps] ACT @ (0, 6084) ->
|
|
[ 5000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) ->
|
|
[10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) ->
|
|
[15000 ps] RD @ (4, 608) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 229065100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 688) -> [15000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 229165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 15993) -> [15000 ps] RD @ (0, 600) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14913) -> [15000 ps] RD @ (4, 600) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 229265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 13834) ->
|
|
[15000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12755) -> [10000 ps] ACT @ (0, 11676) ->
|
|
[ 5000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) ->
|
|
[10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) ->
|
|
[15000 ps] RD @ (4, 600) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 229515100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 6280) -> [15000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 229615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5201) -> [15000 ps] RD @ (0, 592) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4121) -> [15000 ps] RD @ (4, 592) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 229715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3042) ->
|
|
[15000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1963) -> [10000 ps] ACT @ (0, 884) ->
|
|
[ 5000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) ->
|
|
[10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 14030) -> [10000 ps] ACT @ (0, 12951) -> [ 5000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 584) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 230035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [15000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 230135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 8634) ->
|
|
[15000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7555) -> [15000 ps] RD @ (0, 576) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 230235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5397) ->
|
|
[10000 ps] ACT @ (4, 4317) -> [ 5000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 230485100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [15000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 230585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14226) ->
|
|
[15000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13147) -> [15000 ps] RD @ (0, 568) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 230685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10989) ->
|
|
[10000 ps] ACT @ (4, 9909) -> [ 5000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 230935100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [15000 ps] RD @ (4, 560) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 231035100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3434) ->
|
|
[15000 ps] RD @ (4, 560) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2355) -> [15000 ps] RD @ (0, 560) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 231135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 197) ->
|
|
[10000 ps] ACT @ (4, 15501) -> [ 5000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 552) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12264) -> [10000 ps] ACT @ (4, 11184) -> [ 5000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 231455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9026) ->
|
|
[15000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [15000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 231555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 6868) -> [15000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5788) -> [15000 ps] RD @ (4, 544) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 231655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 3630) -> [10000 ps] ACT @ (0, 2551) -> [ 5000 ps] RD @ (4, 544) -> [10000 ps] RD @ (0, 544) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 231905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14618) ->
|
|
[15000 ps] RD @ (4, 536) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [15000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 232005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12460) -> [15000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11380) -> [15000 ps] RD @ (4, 536) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 232105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 9222) -> [10000 ps] ACT @ (0, 8143) -> [ 5000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 528) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 232355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3826) ->
|
|
[15000 ps] RD @ (4, 528) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [15000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 232455100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1668) -> [15000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 588) -> [15000 ps] RD @ (4, 528) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 232555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 14814) -> [10000 ps] ACT @ (0, 13735) -> [ 5000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> [ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10497) -> [10000 ps] ACT @ (0, 9418) -> [ 5000 ps] RD @ (4, 520) ->
|
|
[10000 ps] RD @ (0, 520) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [15000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 232875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7260) -> [15000 ps] RD @ (0, 512) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [15000 ps] RD @ (4, 512) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 232975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5101) -> [15000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4022) ->
|
|
[15000 ps] RD @ (0, 512) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 233075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2943) -> [15000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1864) -> [10000 ps] ACT @ (4, 784) -> [ 5000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> [ 2500 ps] NOP -> [ 7500 ps] ACT @ (0, 15010) ->
|
|
[ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [147500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[27500 ps] ACT @ (0, 13931) -> [15000 ps] RD @ (0, 504) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 233845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12852) -> [15000 ps] RD @ (0, 504) ->
|
|
[15000 ps] ACT @ (4, 11772) -> [15000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 233925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10693) -> [15000 ps] RD @ (4, 504) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9614) -> [15000 ps] RD @ (0, 504) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 234025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8535) ->
|
|
[15000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7456) -> [10000 ps] ACT @ (4, 6376) ->
|
|
[ 5000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) ->
|
|
[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) ->
|
|
[15000 ps] RD @ (0, 496) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 234275100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2060) -> [15000 ps] RD @ (0, 496) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 980) -> [15000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 234375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 16285) -> [15000 ps] RD @ (4, 488) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15206) -> [15000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 234475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14127) ->
|
|
[15000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13048) -> [10000 ps] ACT @ (4, 11968) ->
|
|
[ 5000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) ->
|
|
[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 8731) -> [10000 ps] ACT @ (4, 7651) -> [ 5000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 234795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [15000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 234895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3335) ->
|
|
[15000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2255) -> [15000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 234995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 97) ->
|
|
[10000 ps] ACT @ (0, 15402) -> [ 5000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 235245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [15000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 235345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8927) ->
|
|
[15000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7847) -> [15000 ps] RD @ (4, 464) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 235445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5689) ->
|
|
[10000 ps] ACT @ (0, 4610) -> [ 5000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 235695100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [15000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 235795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14519) ->
|
|
[15000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13439) -> [15000 ps] RD @ (4, 456) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 235895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11281) ->
|
|
[10000 ps] ACT @ (0, 10202) -> [ 5000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6964) -> [10000 ps] ACT @ (0, 5885) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) ->
|
|
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 236215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3727) ->
|
|
[15000 ps] RD @ (0, 448) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [15000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 236315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1568) -> [15000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 489) -> [15000 ps] RD @ (0, 448) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 236415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 14715) -> [10000 ps] ACT @ (4, 13635) -> [ 5000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) ->
|
|
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 236665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 9319) ->
|
|
[15000 ps] RD @ (0, 440) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [15000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 236765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 7160) -> [15000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6081) -> [15000 ps] RD @ (0, 432) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 236865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 3923) -> [10000 ps] ACT @ (4, 2843) -> [ 5000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) ->
|
|
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 237115100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14911) ->
|
|
[15000 ps] RD @ (0, 424) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [15000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 237215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12752) -> [15000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11673) -> [15000 ps] RD @ (0, 424) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 237315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 9515) -> [10000 ps] ACT @ (4, 8435) -> [ 5000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5198) -> [10000 ps] ACT @ (4, 4118) -> [ 5000 ps] RD @ (0, 416) ->
|
|
[10000 ps] RD @ (4, 416) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 237635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [15000 ps] RD @ (0, 416) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 237735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 16186) -> [15000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15106) ->
|
|
[15000 ps] RD @ (4, 408) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 237835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12948) -> [10000 ps] ACT @ (0, 11869) -> [ 5000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> [10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) ->
|
|
[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [15000 ps] RD @ (4, 408) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 238085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 7552) -> [15000 ps] RD @ (4, 400) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [15000 ps] RD @ (0, 400) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 238185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5394) -> [15000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4314) ->
|
|
[15000 ps] RD @ (4, 400) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 238285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2156) -> [10000 ps] ACT @ (0, 1077) -> [ 5000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) -> [ 5000 ps] RD @ (0, 392) ->
|
|
[10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 238535100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [15000 ps] RD @ (0, 392) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 238635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10986) -> [15000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9906) ->
|
|
[15000 ps] RD @ (4, 392) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 238735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7748) -> [10000 ps] ACT @ (0, 6669) -> [ 5000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) -> [ 5000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (4, 384) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3431) -> [10000 ps] ACT @ (0, 2352) ->
|
|
[ 5000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 239055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 194) -> [15000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) ->
|
|
[15000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 239155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14419) -> [15000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 13340) -> [15000 ps] RD @ (0, 376) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 239255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11182) -> [10000 ps] ACT @ (4, 10102) -> [ 5000 ps] RD @ (0, 376) ->
|
|
[10000 ps] RD @ (4, 376) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) -> [10000 ps] ACT @ (0, 7944) ->
|
|
[ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 239505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5786) -> [15000 ps] RD @ (0, 368) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) ->
|
|
[15000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 239605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3627) -> [15000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 2548) -> [15000 ps] RD @ (0, 368) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 239705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 390) -> [10000 ps] ACT @ (4, 15694) -> [ 5000 ps] RD @ (0, 368) ->
|
|
[10000 ps] RD @ (4, 360) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) ->
|
|
[ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 239955100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) ->
|
|
[15000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 240055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9219) -> [15000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 8140) -> [15000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 240155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5982) -> [10000 ps] ACT @ (4, 4902) -> [ 5000 ps] RD @ (0, 352) ->
|
|
[10000 ps] RD @ (4, 352) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) ->
|
|
[ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1665) ->
|
|
[10000 ps] ACT @ (4, 585) -> [ 5000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) ->
|
|
[15000 ps] RD @ (4, 344) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 240475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 13732) -> [15000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 240575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12653) -> [15000 ps] RD @ (0, 344) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11573) -> [15000 ps] RD @ (4, 344) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 240675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10494) ->
|
|
[15000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9415) -> [10000 ps] ACT @ (0, 8336) ->
|
|
[ 5000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) ->
|
|
[10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) ->
|
|
[15000 ps] RD @ (4, 336) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 240925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 2940) -> [15000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 241025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1861) -> [15000 ps] RD @ (0, 336) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 781) -> [15000 ps] RD @ (4, 336) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 241125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 16086) ->
|
|
[15000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15007) -> [10000 ps] ACT @ (0, 13928) ->
|
|
[ 5000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) ->
|
|
[10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) ->
|
|
[15000 ps] RD @ (4, 328) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 241375100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 8532) -> [15000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 241475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7453) -> [15000 ps] RD @ (0, 320) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6373) -> [15000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 241575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5294) ->
|
|
[ 2500 ps] NOP -> [12500 ps] RD @ (4, 320) -> [157500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[27500 ps] ACT @ (4, 4215) -> [10000 ps] ACT @ (0, 3136) -> [ 5000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16282) -> [10000 ps] ACT @ (0, 15203) -> [ 5000 ps] RD @ (4, 312) ->
|
|
[10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 242425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [15000 ps] RD @ (4, 312) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 242525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 10886) -> [15000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9807) ->
|
|
[15000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 242625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7649) -> [10000 ps] ACT @ (4, 6569) -> [ 5000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) ->
|
|
[10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 242875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) -> [15000 ps] RD @ (4, 304) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 242975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 94) -> [15000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15399) ->
|
|
[15000 ps] RD @ (0, 296) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 243075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13241) -> [10000 ps] ACT @ (4, 12161) -> [ 5000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) ->
|
|
[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 243325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [15000 ps] RD @ (4, 288) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 243425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5686) -> [15000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4607) ->
|
|
[15000 ps] RD @ (0, 288) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 243525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2449) -> [10000 ps] ACT @ (4, 1369) -> [ 5000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) ->
|
|
[10000 ps] RD @ (0, 280) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14516) -> [10000 ps] ACT @ (4, 13436) ->
|
|
[ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 243845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) ->
|
|
[15000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 243945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 9120) -> [15000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8040) -> [15000 ps] RD @ (4, 272) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 244045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5882) -> [10000 ps] ACT @ (0, 4803) -> [ 5000 ps] RD @ (4, 272) ->
|
|
[10000 ps] RD @ (0, 272) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) ->
|
|
[ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 244295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) ->
|
|
[15000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 244395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14712) -> [15000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 13632) -> [15000 ps] RD @ (4, 264) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 244495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11474) -> [10000 ps] ACT @ (0, 10395) -> [ 5000 ps] RD @ (4, 264) ->
|
|
[10000 ps] RD @ (0, 264) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) ->
|
|
[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 244745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) ->
|
|
[15000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 244845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3920) -> [15000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 2840) -> [15000 ps] RD @ (4, 256) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 244945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 682) -> [10000 ps] ACT @ (0, 15987) -> [ 5000 ps] RD @ (4, 256) ->
|
|
[10000 ps] RD @ (0, 248) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) ->
|
|
[ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12749) ->
|
|
[10000 ps] ACT @ (0, 11670) -> [ 5000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) ->
|
|
[15000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 245265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8432) -> [15000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 245365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 7353) -> [15000 ps] RD @ (4, 240) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6274) -> [15000 ps] RD @ (0, 240) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 245465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5195) ->
|
|
[15000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4116) -> [10000 ps] ACT @ (4, 3036) ->
|
|
[ 5000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) ->
|
|
[10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) ->
|
|
[15000 ps] RD @ (0, 232) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 245715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14024) -> [15000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 245815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12945) -> [15000 ps] RD @ (4, 232) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11866) -> [15000 ps] RD @ (0, 232) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 245915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10787) ->
|
|
[15000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9708) -> [10000 ps] ACT @ (4, 8628) ->
|
|
[ 5000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) ->
|
|
[10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) ->
|
|
[15000 ps] RD @ (0, 224) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 246165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3232) -> [15000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 246265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 2153) -> [15000 ps] RD @ (4, 224) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1074) -> [15000 ps] RD @ (0, 224) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 246365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 16379) ->
|
|
[15000 ps] RD @ (0, 216) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15300) -> [10000 ps] ACT @ (4, 14220) ->
|
|
[ 5000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) ->
|
|
[10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 10983) -> [10000 ps] ACT @ (4, 9903) -> [ 5000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 246685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [15000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 246785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5587) ->
|
|
[15000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4507) -> [15000 ps] RD @ (4, 208) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 246885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2349) ->
|
|
[10000 ps] ACT @ (0, 1270) -> [ 5000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 247135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [15000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 247235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 11179) ->
|
|
[15000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10099) -> [15000 ps] RD @ (4, 200) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 247335100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7941) ->
|
|
[10000 ps] ACT @ (0, 6862) -> [ 5000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 247585100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) ->
|
|
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [15000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 247685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 387) ->
|
|
[15000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15691) -> [15000 ps] RD @ (4, 184) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 247785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13533) ->
|
|
[10000 ps] ACT @ (0, 12454) -> [ 5000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9216) -> [10000 ps] ACT @ (0, 8137) -> [ 5000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) ->
|
|
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 248105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5979) ->
|
|
[15000 ps] RD @ (0, 176) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [15000 ps] RD @ (4, 176) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 248205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 3820) -> [15000 ps] RD @ (4, 176) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2741) -> [15000 ps] RD @ (0, 176) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 248305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 583) -> [10000 ps] ACT @ (4, 15887) -> [ 5000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) ->
|
|
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 248555100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 11571) ->
|
|
[15000 ps] RD @ (0, 168) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [15000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 248655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9412) -> [15000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8333) -> [15000 ps] RD @ (0, 168) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 248755100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 6175) -> [10000 ps] ACT @ (4, 5095) -> [ 5000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> [10000 ps] RD @ (0, 160) ->
|
|
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 249005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 779) ->
|
|
[15000 ps] RD @ (0, 160) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [15000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 249105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15004) -> [15000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13925) -> [15000 ps] RD @ (0, 152) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 249205100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 11767) -> [10000 ps] ACT @ (4, 10687) -> [ 5000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7450) -> [10000 ps] ACT @ (4, 6370) -> [ 5000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 249525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [15000 ps] RD @ (0, 144) ->
|
|
[17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 249625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2054) -> [15000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 974) ->
|
|
[15000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 249725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15200) -> [10000 ps] ACT @ (0, 14121) -> [ 5000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) ->
|
|
[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> [ 5000 ps] RD @ (0, 136) ->
|
|
[10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> [ 7500 ps] NOP ->
|
|
[10000 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 249975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> [127500 ps] PRE @ (0) -> [30000 ps] REF ->
|
|
[360000 ps] NOP -> [17500 ps] ACT @ (0, 8725) -> [15000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 250575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 7646) ->
|
|
[15000 ps] RD @ (0, 128) -> [15000 ps] ACT @ (4, 6566) -> [15000 ps] RD @ (4, 128) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 250655100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5487) ->
|
|
[15000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4408) -> [10000 ps] ACT @ (0, 3329) ->
|
|
[ 5000 ps] RD @ (4, 128) -> [10000 ps] RD @ (0, 128) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) ->
|
|
[10000 ps] ACT @ (4, 1170) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) ->
|
|
[15000 ps] RD @ (4, 128) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 250905100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> [17500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 14317) -> [15000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 251005100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 13238) -> [15000 ps] RD @ (0, 120) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12158) -> [15000 ps] RD @ (4, 120) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 251105100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11079) ->
|
|
[15000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10000) -> [10000 ps] ACT @ (0, 8921) ->
|
|
[ 5000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) ->
|
|
[10000 ps] ACT @ (4, 6762) -> [ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 5683) -> [10000 ps] ACT @ (0, 4604) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 3525) -> [15000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 251425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 2446) -> [15000 ps] RD @ (0, 112) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [15000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 251525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 287) ->
|
|
[15000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15592) -> [15000 ps] RD @ (0, 104) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 251625100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14513) -> [15000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13434) ->
|
|
[10000 ps] ACT @ (4, 12354) -> [ 5000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9117) -> [15000 ps] RD @ (0, 104) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 251875100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 8038) -> [15000 ps] RD @ (0, 96) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [15000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 251975100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 5879) ->
|
|
[15000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4800) -> [15000 ps] RD @ (0, 96) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 252075100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 3721) -> [15000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2642) ->
|
|
[10000 ps] ACT @ (4, 1562) -> [ 5000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 483) -> [10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 14709) -> [15000 ps] RD @ (0, 88) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 252325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 13630) -> [15000 ps] RD @ (0, 88) ->
|
|
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [15000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 252425100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11471) ->
|
|
[15000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10392) -> [15000 ps] RD @ (0, 88) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 252525100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 9313) -> [15000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8234) ->
|
|
[10000 ps] ACT @ (4, 7154) -> [ 5000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6075) -> [10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3917) -> [10000 ps] ACT @ (4, 2837) -> [ 5000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 252845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 679) ->
|
|
[15000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [15000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 252945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 14905) -> [15000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13825) -> [15000 ps] RD @ (4, 72) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 253045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 11667) -> [10000 ps] ACT @ (0, 10588) -> [ 5000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 253295100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 6271) ->
|
|
[15000 ps] RD @ (4, 64) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [15000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 253395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 4113) -> [15000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3033) -> [15000 ps] RD @ (4, 64) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 253495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 875) -> [10000 ps] ACT @ (0, 16180) -> [ 5000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) ->
|
|
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 253745100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 11863) ->
|
|
[15000 ps] RD @ (4, 56) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [15000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 253845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 9705) -> [15000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8625) -> [15000 ps] RD @ (4, 56) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 253945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6467) -> [10000 ps] ACT @ (0, 5388) -> [ 5000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2150) -> [10000 ps] ACT @ (0, 1071) -> [ 5000 ps] RD @ (4, 48) ->
|
|
[10000 ps] RD @ (0, 48) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 254265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [15000 ps] RD @ (4, 40) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 254365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 13138) -> [15000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12059) ->
|
|
[15000 ps] RD @ (0, 40) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 254465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9901) -> [10000 ps] ACT @ (4, 8821) -> [ 5000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) ->
|
|
[10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 254715100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [15000 ps] RD @ (4, 32) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 254815100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 2346) -> [15000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1267) ->
|
|
[15000 ps] RD @ (0, 32) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 254915100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15493) -> [10000 ps] ACT @ (4, 14413) -> [ 5000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) ->
|
|
[10000 ps] RD @ (0, 24) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [17500 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 255165100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [15000 ps] RD @ (4, 24) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 255265100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 7938) -> [15000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6859) ->
|
|
[15000 ps] RD @ (0, 16) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 255365100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4701) -> [10000 ps] ACT @ (4, 3621) -> [ 5000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) ->
|
|
[10000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 384) -> [10000 ps] ACT @ (4, 15688) ->
|
|
[ 5000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 255685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) ->
|
|
[15000 ps] RD @ (0, 8) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 255785100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 11372) -> [15000 ps] RD @ (0, 8) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 10292) -> [15000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 255885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) ->
|
|
[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8134) -> [10000 ps] ACT @ (0, 7055) -> [ 5000 ps] RD @ (4, 0) ->
|
|
[10000 ps] RD @ (0, 0) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) ->
|
|
[ 5000 ps] RD @ (0, 0) -> [10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) ->
|
|
[17500 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256135100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) ->
|
|
[15000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256235100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [25000 ps] ACT @ (7, 15884) ->
|
|
[ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 1016) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256325100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) ->
|
|
[15000 ps] ACT @ (0, 13727) -> [12500 ps] PRE @ (7) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (7, 13726) -> [10000 ps] ACT @ (4, 12647) ->
|
|
[ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (3, 12647) -> [15000 ps] RD @ (3, 1016) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (3, 11568) -> [10000 ps] ACT @ (0, 10489) -> [ 5000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 10488) -> [15000 ps] RD @ (7, 1016) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) ->
|
|
[10000 ps] ACT @ (7, 9409) -> [15000 ps] RD @ (7, 1016) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256615100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) ->
|
|
[15000 ps] ACT @ (4, 7251) -> [12500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256685100.0 ps ERROR: tRAS minimum violation during Precharge to bank 4
|
|
[ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256702600.0 ps ERROR: tRC violation during Activate to bank 4
|
|
[ 5000 ps] RD @ (3, 1008) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256725100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [17500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 4014) -> [10000 ps] ACT @ (7, 5092) -> [15000 ps] RD @ (7, 1008) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 256835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 4013) -> [15000 ps] RD @ (7, 1008) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (7, 2934) -> [10000 ps] ACT @ (4, 1855) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) ->
|
|
[15000 ps] RD @ (3, 1008) -> [17500 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) ->
|
|
[15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16080) -> [15000 ps] RD @ (7, 1000) -> [17500 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 13922) -> [15000 ps] RD @ (3, 1000) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) ->
|
|
[10000 ps] ACT @ (3, 12843) -> [15000 ps] RD @ (3, 1000) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) ->
|
|
[15000 ps] ACT @ (0, 10685) -> [12500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257332600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
[ 5000 ps] RD @ (7, 1000) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257355100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [17500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 7447) -> [10000 ps] ACT @ (3, 8526) -> [15000 ps] RD @ (3, 1000) -> [17500 ps] PRE @ (3) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257465100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 7447) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (3, 6368) -> [10000 ps] ACT @ (0, 5289) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5288) ->
|
|
[15000 ps] RD @ (7, 992) -> [17500 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3130) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) ->
|
|
[15000 ps] RD @ (7, 992) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3130) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (3) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257775100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> [15000 ps] ACT @ (0, 16277) -> [12500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 0
|
|
[ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257862600.0 ps ERROR: tRC violation during Activate to bank 0
|
|
[ 5000 ps] RD @ (7, 984) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257885100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 15197) ->
|
|
[15000 ps] RD @ (7, 984) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 13039) -> [10000 ps] ACT @ (3, 14118) ->
|
|
[15000 ps] RD @ (3, 984) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 257995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 13039) -> [15000 ps] RD @ (3, 984) -> [17500 ps] PRE @ (4) ->
|
|
[10000 ps] PRE @ (3) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (3, 11960) -> [10000 ps] ACT @ (0, 10881) -> [ 5000 ps] RD @ (3, 984) ->
|
|
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10880) -> [15000 ps] RD @ (7, 984) -> [17500 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8722) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) ->
|
|
[15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [17500 ps] PRE @ (3) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 258305100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 6564) -> [12500 ps] NOP -> [ 2500 ps] RD @ (3, 976) -> [167500 ps] PRE @ (0) -> [30000 ps] REF ->
|
|
[360000 ps] NOP -> [17500 ps] ACT @ (7, 5484) -> [15000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 258945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 4405) ->
|
|
[15000 ps] RD @ (7, 976) -> [15000 ps] ACT @ (3, 3326) -> [15000 ps] RD @ (3, 976) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 259025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 2247) ->
|
|
[15000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1168) -> [10000 ps] ACT @ (7, 88) ->
|
|
[ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) ->
|
|
[10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 13235) -> [10000 ps] ACT @ (7, 12155) -> [ 5000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [27500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 259345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) ->
|
|
[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [15000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 259445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 7839) ->
|
|
[15000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6759) -> [15000 ps] RD @ (7, 960) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 259545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4601) ->
|
|
[10000 ps] ACT @ (3, 3522) -> [ 5000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 259795100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) ->
|
|
[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [15000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 259895100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 13431) ->
|
|
[15000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12351) -> [15000 ps] RD @ (7, 952) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 259995100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10193) ->
|
|
[10000 ps] ACT @ (3, 9114) -> [ 5000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 260245100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) ->
|
|
[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [15000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 260345100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 2639) ->
|
|
[15000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1559) -> [15000 ps] RD @ (7, 944) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 260445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15785) ->
|
|
[10000 ps] ACT @ (3, 14706) -> [ 5000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11468) -> [10000 ps] ACT @ (3, 10389) -> [ 5000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) ->
|
|
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 260765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 8231) ->
|
|
[15000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [15000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 260865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 6072) -> [15000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4993) -> [15000 ps] RD @ (3, 928) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 260965100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 2835) -> [10000 ps] ACT @ (7, 1755) -> [ 5000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) ->
|
|
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 261215100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 13823) ->
|
|
[15000 ps] RD @ (3, 920) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [15000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 261315100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 11664) -> [15000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10585) -> [15000 ps] RD @ (3, 920) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 261415100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 8427) -> [10000 ps] ACT @ (7, 7347) -> [ 5000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) ->
|
|
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 261665100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 3031) ->
|
|
[15000 ps] RD @ (3, 912) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [15000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 261765100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 872) -> [15000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16177) -> [15000 ps] RD @ (3, 904) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 261865100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 14019) -> [10000 ps] ACT @ (7, 12939) -> [ 5000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) ->
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9702) -> [10000 ps] ACT @ (7, 8622) -> [ 5000 ps] RD @ (3, 904) ->
|
|
[10000 ps] RD @ (7, 904) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 262185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [15000 ps] RD @ (3, 896) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 262285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 4306) -> [15000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3226) ->
|
|
[15000 ps] RD @ (7, 896) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 262385100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1068) -> [10000 ps] ACT @ (3, 16373) -> [ 5000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) ->
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) ->
|
|
[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 262635100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [15000 ps] RD @ (3, 888) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 262735100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 9898) -> [15000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8818) ->
|
|
[15000 ps] RD @ (7, 888) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 262835100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6660) -> [10000 ps] ACT @ (3, 5581) -> [ 5000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) ->
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) ->
|
|
[10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 263085100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [15000 ps] RD @ (3, 880) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 263185100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 15490) -> [15000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14410) ->
|
|
[15000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 263285100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12252) -> [10000 ps] ACT @ (3, 11173) -> [ 5000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) ->
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) ->
|
|
[10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 7935) -> [10000 ps] ACT @ (3, 6856) ->
|
|
[ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 263605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) ->
|
|
[15000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 263705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 2539) -> [15000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 1460) -> [15000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 263805100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) ->
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15686) -> [10000 ps] ACT @ (7, 14606) -> [ 5000 ps] RD @ (3, 856) ->
|
|
[10000 ps] RD @ (7, 856) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) ->
|
|
[ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 264055100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) ->
|
|
[15000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 264155100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 8131) -> [15000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 7052) -> [15000 ps] RD @ (3, 848) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 264255100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) ->
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4894) -> [10000 ps] ACT @ (7, 3814) -> [ 5000 ps] RD @ (3, 848) ->
|
|
[10000 ps] RD @ (7, 848) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) ->
|
|
[ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 264505100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) ->
|
|
[15000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 264605100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 13723) -> [15000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 12644) -> [15000 ps] RD @ (3, 840) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 264705100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) ->
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10486) -> [10000 ps] ACT @ (7, 9406) -> [ 5000 ps] RD @ (3, 840) ->
|
|
[10000 ps] RD @ (7, 840) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) ->
|
|
[ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6169) ->
|
|
[10000 ps] ACT @ (7, 5089) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) ->
|
|
[15000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 265025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 1852) -> [15000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 265125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 773) -> [15000 ps] RD @ (3, 832) ->
|
|
[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16077) -> [15000 ps] RD @ (7, 824) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 265225100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 14998) ->
|
|
[15000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13919) -> [10000 ps] ACT @ (3, 12840) ->
|
|
[ 5000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) ->
|
|
[10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) ->
|
|
[15000 ps] RD @ (7, 824) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 265475100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [17500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 7444) -> [15000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 265575100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 6365) -> [15000 ps] RD @ (3, 816) ->
|
|
[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5285) -> [15000 ps] RD @ (7, 816) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 265675100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 4206) ->
|
|
[15000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3127) -> [10000 ps] ACT @ (3, 2048) ->
|
|
[ 5000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) ->
|
|
[10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) ->
|
|
[15000 ps] RD @ (7, 808) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 265925100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [17500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 13036) -> [15000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 266025100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 11957) -> [15000 ps] RD @ (3, 808) ->
|
|
[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10877) -> [15000 ps] RD @ (7, 808) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 266125100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 9798) ->
|
|
[15000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8719) -> [10000 ps] ACT @ (3, 7640) ->
|
|
[ 5000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) ->
|
|
[10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
|
|
[ 7500 ps] ACT @ (7, 4402) -> [10000 ps] ACT @ (3, 3323) -> [ 5000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [27500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 266445100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) ->
|
|
[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [15000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 266545100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 15390) ->
|
|
[15000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14311) -> [15000 ps] RD @ (3, 792) -> [17500 ps] PRE @ (3) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 266645100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12153) ->
|
|
[10000 ps] ACT @ (7, 11073) -> [ 5000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> [127500 ps] PRE @ (0) -> [30000 ps] REF ->
|
|
[360000 ps] NOP -> [27500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) ->
|
|
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 267395100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 6757) ->
|
|
[15000 ps] RD @ (3, 784) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [15000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 267495100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 4598) -> [15000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3519) -> [15000 ps] RD @ (3, 784) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 267595100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 1361) -> [10000 ps] ACT @ (7, 281) -> [ 5000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [27500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) ->
|
|
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 267845100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 12349) ->
|
|
[15000 ps] RD @ (3, 776) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [15000 ps] RD @ (7, 776) -> [17500 ps] PRE @ (7) ->
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 267945100.0 ps ERROR: tRAS minimum violation during Precharge to bank 7
|
|
[17500 ps] ACT @ (7, 10190) -> [15000 ps] RD @ (7, 776) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9111) -> [15000 ps] RD @ (3, 776) ->
|
|
[17500 ps] PRE @ (3) -> ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 268045100.0 ps ERROR: tRAS minimum violation during Precharge to bank 3
|
|
[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) ->
|
|
DONE TEST 1: LAST ROW
|
|
|
|
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 6953) -> [10000 ps] ACT @ (7, 5873) -> [ 5000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) ->
|
|
|
|
------- SUMMARY -------
|
|
Number of Writes = 4608
|
|
Number of Reads = 4608
|
|
Number of Success = 4608
|
|
Number of Fails = 0
|
|
|
|
$stop called at time : 269190 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 387
|
|
run: Time (s): cpu = 00:17:20 ; elapsed = 00:51:01 . Memory (MB): peak = 7646.273 ; gain = 18.098 ; free physical = 346 ; free virtual = 23179
|