UberDDR3/rtl
AngeloJacobo b0e3b83e96 added wb properties from zipcpu repo 2023-06-22 19:54:39 +08:00
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ddr3_controller.v add logic for write wb_ack, wb_sel, and aux 2023-06-22 19:49:05 +08:00
ddr3_phy.v add phy for data mask (oserdes -> odelay -> obuf) 2023-06-22 19:51:06 +08:00
ddr3_top.v add data mask port 2023-06-22 19:52:45 +08:00
fwb_slave.v added wb properties from zipcpu repo 2023-06-22 19:54:39 +08:00