AngeloJacobo d5f1d600ea resolve verilator warnings and add option YOSYS for not using input real in functions		2023-07-24 17:27:17 +08:00
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ddr3_controller.v	resolve verilator warnings and add option YOSYS for not using input real in functions	2023-07-24 17:27:17 +08:00
ddr3_phy.v	resolved warning from vivado on IOBDELAY	2023-07-19 18:47:24 +08:00
ddr3_top.v	less simulation warning	2023-07-19 18:48:31 +08:00
fwb_slave.v	make stall and accessible outside, removed added assumptions with i_slave_busy	2023-07-13 18:48:34 +08:00