AngeloJacobo e19c6023c4 remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing		2025-03-01 15:51:48 +08:00
..
axi	update UberDDR3 AXI for Vivado custom IP	2025-02-16 14:53:05 +08:00
ecc	Revert "add self-refresh option, passing Simulation, ongoing formal"	2024-11-23 11:43:05 +08:00
spd	added simulation and project demo with XADC	2025-01-12 14:55:43 +08:00
ddr3_controller.v	remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing	2025-03-01 15:51:48 +08:00
ddr3_phy.v	added IODELAY_GROUP for ODELAY,IDELAY,and IDELAYCTRL	2025-03-01 14:41:00 +08:00
ddr3_top.v	add xdc for microblaze run, and minor fixes in params	2025-02-22 11:23:24 +08:00