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luke
/
UberDDR3
mirror of
https://github.com/AngeloJacobo/UberDDR3.git
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de4fb994b4
UberDDR3
/
rtl
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AngeloJacobo
de4fb994b4
add debug lines and update wb2 registers
2023-09-05 20:17:10 +08:00
..
ddr3_controller.v
add debug lines and update wb2 registers
2023-09-05 20:17:10 +08:00
ddr3_phy.v
add dci reset and optional DCIEN IO buffers
2023-09-05 18:32:30 +08:00
ddr3_top.v
add wire for cue when write leveling starts
2023-09-05 18:33:20 +08:00
fwb_slave.v
make stall and accessible outside, removed added assumptions with i_slave_busy
2023-07-13 18:48:34 +08:00