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UberDDR3
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UberDDR3/example_demo/arty_s7
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AngeloJacobo 339adfe8d6 added simulation and project demo with XADC 2025-01-12 14:55:43 +08:00
..
Makefile add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00
arty_ddr3.v added simulation and project demo with XADC 2025-01-12 14:55:43 +08:00
arty_ddr3.xdc added simulation and project demo with XADC 2025-01-12 14:55:43 +08:00
clk_wiz.v replace clock wizard with PLL 2024-06-09 15:31:27 +08:00
uart_rx.v add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00
uart_tx.v add makefile for openxc7 run (WORKING) 2024-10-13 16:45:06 +08:00