623 lines
20 KiB
Verilog
623 lines
20 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ./toplevel.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// DO NOT EDIT THIS FILE!
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// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
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// DO NOT EDIT THIS FILE!
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//
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// CmdLine: autofpga autofpga -I .: -d -o . allclocks.txt global.txt wbdown.txt icape.txt version.txt gpio.txt spio.txt wbuconsole.txt zipmaster.txt bkram.txt ddr3.txt sdio.txt emmc.txt sdioscope.txt emmcscope.txt mem_bkram_only.txt mem_flash_bkram.txt i2ccpu.txt fan.txt sirefclk.txt i2cscope.txt
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, files
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// }}}
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`default_nettype none
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//
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// Here we declare our toplevel.v (toplevel) design module.
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// All design logic must take place beneath this top level.
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//
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// The port declarations just copy data from the @TOP.PORTLIST
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// key, or equivalently from the @MAIN.PORTLIST key if
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// @TOP.PORTLIST is absent. For those peripherals that don't need
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// any top level logic, the @MAIN.PORTLIST should be sufficent,
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// so the @TOP.PORTLIST key may be left undefined.
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//
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// The only exception is that any clocks with CLOCK.TOP tags will
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// also appear in this list
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//
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module toplevel(
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// DDR3 I/O port wires
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o_ddr3_reset_n, o_ddr3_cke, o_ddr3_clk_p, o_ddr3_clk_n,
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o_ddr3_s_n, o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n,
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o_ddr3_ba, o_ddr3_a,
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o_ddr3_odt, o_ddr3_dm,
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io_ddr3_dqs_p, io_ddr3_dqs_n, io_ddr3_dq,
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o_siref_clk_p, o_siref_clk_n,
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io_temp_sda, io_temp_scl,
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o_fan_pwm, o_fan_sys, i_fan_tach,
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// eMMC Card
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// o_emmc_clk,
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io_emmc_cmd, io_emmc_dat, i_emmc_ds,
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io_i2c_sda, io_i2c_scl,
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o_i2c_mxrst_n,
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// SDIO SD Card
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o_sdcard_clk, io_sdcard_cmd, io_sdcard_dat, i_sdcard_cd_n,
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i_clk_200mhz_p, i_clk_200mhz_n,
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// UART/host to wishbone interface
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i_wbu_uart_rx, o_wbu_uart_tx,
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o_wbu_uart_cts_n,
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// GPIO ports
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i_pi_reset_n, i_soft_reset, i_hdmitx_hpd_n,
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o_tp, o_si5324_rst, i_si5324_int,
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o_hdmirx_hpd_n,
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// SPIO interface
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i_sw, i_nbtn_u, i_nbtn_l, i_nbtn_c, i_nbtn_r, i_nbtn_d, o_led);
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//
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// Declaring any top level parameters.
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//
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// These declarations just copy data from the @TOP.PARAM key,
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// or from the @MAIN.PARAM key if @TOP.PARAM is absent. For
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// those peripherals that don't do anything at the top level,
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// the @MAIN.PARAM key should be sufficient, so the @TOP.PARAM
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// key may be left undefined.
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//
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localparam real DDR3_CONTROLLERCONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device
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localparam DDR3_CONTROLLERROW_BITS = 14, // width of row address
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DDR3_CONTROLLERCOL_BITS = 10, // width of column address
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DDR3_CONTROLLERBA_BITS = 3, // width of bank address
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DDR3_CONTROLLERDQ_BITS = 8, // Size of one octet
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DDR3_CONTROLLERLANES = 8, //8 lanes of DQ
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DDR3_CONTROLLERAUX_WIDTH = 1,
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DDR3_CONTROLLERSERDES_RATIO = $rtoi(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
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//4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
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DDR3_CONTROLLERCMD_LEN = 4 + 3 + DDR3_CONTROLLERBA_BITS + DDR3_CONTROLLERROW_BITS;
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////////////////////////////////////////////////////////////////////////
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//
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// Variables/definitions/parameters used by the ZipCPU bus master
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// {{{
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//
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// A 32-bit address indicating where the ZipCPU should start running
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// from
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`ifdef BKROM_ACCESS
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localparam RESET_ADDRESS = @$(/bkrom.BASE);
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`else
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`ifdef FLASH_ACCESS
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localparam RESET_ADDRESS = @$RESET_ADDRESS;
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`else
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localparam RESET_ADDRESS = 67108864;
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`endif // FLASH_ACCESS
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`endif // BKROM_ACCESS
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//
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// The number of valid bits on the bus
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localparam ZIP_ADDRESS_WIDTH = 22; // Zip-CPU address width
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//
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// Number of ZipCPU interrupts
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localparam ZIP_INTS = 16;
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//
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// ZIP_START_HALTED
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//
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// A boolean, indicating whether or not the ZipCPU be halted on startup?
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`ifdef BKROM_ACCESS
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localparam ZIP_START_HALTED=1'b0;
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`else
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localparam ZIP_START_HALTED=1'b1;
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`endif
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// }}}
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////////////////////////////////////////////////////////////////////////
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//
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// WBUBUS parameters
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// {{{
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// Baudrate : 1000000
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// Clock : 100000000
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localparam [23:0] BUSUART = 24'h64; // 1000000 baud
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localparam DBGBUSBITS = $clog2(BUSUART);
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//
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// Maximum command is 6 bytes, where each byte takes 10 baud clocks
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// and each baud clock requires DBGBUSBITS to represent. Here,
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// we'll add one more for good measure.
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localparam DBGBUSWATCHDOG_RAW = DBGBUSBITS + 9;
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localparam DBGBUSWATCHDOG = (DBGBUSWATCHDOG_RAW > 19)
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? DBGBUSWATCHDOG_RAW : 19;
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// }}}
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localparam ICAPE_LGDIV=3;
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//
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// Declaring our input and output ports. We listed these above,
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// now we are declaring them here.
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//
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// These declarations just copy data from the @TOP.IODECLS key,
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// or from the @MAIN.IODECL key if @TOP.IODECL is absent. For
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// those peripherals that don't do anything at the top level,
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// the @MAIN.IODECL key should be sufficient, so the @TOP.IODECL
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// key may be left undefined.
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//
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// We start with any @CLOCK.TOP keys
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//
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// I/O declarations for the DDR3 SDRAM
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// {{{
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output wire o_ddr3_reset_n;
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output wire [1:0] o_ddr3_cke;
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output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n;
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output wire [1:0] o_ddr3_s_n; // o_ddr3_s_n[1] is set to 0 since controller only support single rank
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output wire [0:0] o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n;
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output wire [DDR3_CONTROLLERBA_BITS-1:0] o_ddr3_ba;
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output wire [15:0] o_ddr3_a; //set to max of 16 bits, but only ROW_BITS bits are relevant
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output wire [1:0] o_ddr3_odt;
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output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_dm;
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inout wire [(DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES)/8-1:0] io_ddr3_dqs_p, io_ddr3_dqs_n;
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inout wire [(DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES)-1:0] io_ddr3_dq;
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// }}}
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output wire o_siref_clk_p, o_siref_clk_n;
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inout wire io_temp_sda, io_temp_scl;
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output wire o_fan_pwm, o_fan_sys;
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input wire i_fan_tach;
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// eMMC Card
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// {{{
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// output wire o_emmc_clk;
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inout wire io_emmc_cmd;
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inout wire [8-1:0] io_emmc_dat;
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input wire i_emmc_ds;
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// }}}
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inout wire io_i2c_sda, io_i2c_scl;
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output wire o_i2c_mxrst_n;
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// SDIO SD Card
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// {{{
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output wire o_sdcard_clk;
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inout wire io_sdcard_cmd;
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inout wire [4-1:0] io_sdcard_dat;
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input wire i_sdcard_cd_n;
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// }}}
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input wire i_clk_200mhz_p, i_clk_200mhz_n;
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input wire i_wbu_uart_rx;
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output wire o_wbu_uart_tx;
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// input wire i_wbu_uart_rts_n; // FT*'s perspective
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output wire o_wbu_uart_cts_n;
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// GPIO wires
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input wire i_pi_reset_n, i_soft_reset, i_hdmitx_hpd_n;
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output wire [3:0] o_tp;
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output wire o_si5324_rst, o_hdmirx_hpd_n;
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input wire i_si5324_int;
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// SPIO interface
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input wire [8-1:0] i_sw;
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input wire i_nbtn_c, i_nbtn_d, i_nbtn_l, i_nbtn_r, i_nbtn_u;
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output wire [8-1:0] o_led;
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//
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// Declaring component data, internal wires and registers
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//
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// These declarations just copy data from the @TOP.DEFNS key
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// within the component data files.
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//
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// Wires connected to PHY interface of DDR3 controller
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// {{{
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genvar ddr3_controllergen_index;
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wire [DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES*8-1:0] ddr3_controller_iserdes_data;
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wire [DDR3_CONTROLLERLANES*8-1:0] ddr3_controller_iserdes_dqs;
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wire [DDR3_CONTROLLERLANES*8-1:0] ddr3_controller_iserdes_bitslip_reference;
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wire ddr3_controller_idelayctrl_rdy;
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wire [DDR3_CONTROLLERCMD_LEN*DDR3_CONTROLLERSERDES_RATIO-1:0] ddr3_controller_cmd;
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wire ddr3_controller_dqs_tri_control, ddr3_controller_dq_tri_control;
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wire ddr3_controller_toggle_dqs;
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wire [512-1:0] ddr3_controller_data;
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wire [512/8-1:0] ddr3_controller_dm;
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wire [4:0] ddr3_controller_odelay_data_cntvaluein, ddr3_controller_odelay_dqs_cntvaluein;
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wire [4:0] ddr3_controller_idelay_data_cntvaluein, ddr3_controller_idelay_dqs_cntvaluein;
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wire [DDR3_CONTROLLERLANES-1:0] ddr3_controller_odelay_data_ld, ddr3_controller_odelay_dqs_ld;
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wire [DDR3_CONTROLLERLANES-1:0] ddr3_controller_idelay_data_ld, ddr3_controller_idelay_dqs_ld;
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wire [DDR3_CONTROLLERLANES-1:0] ddr3_controller_bitslip;
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// }}}
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// Definitions for the clock generation circuit
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wire s_sirefclk_clk, w_sirefclk_pll_locked,
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w_sirefclk_ce;
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wire s_clk4x; // s_clk4x_unbuffered,
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// s_clksync, s_clksync_unbuffered;
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wire [7:0] w_sirefclk_word;
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// FAN definitions
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// {{{
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wire i_fan_sda, i_fan_scl,
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o_fan_sda, o_fan_scl;
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// }}}
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// eMMC Card definitions
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// {{{
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wire i_emmc_cd_n;
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wire o_emmc_clk;
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// }}}
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// I2CCPU definitions
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// {{{
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wire i_i2c_sda, i_i2c_scl,
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o_i2c_sda, o_i2c_scl;
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reg r_i2c_mxrst_n;
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reg [2:0] r_i2c_mxrst_dly;
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// }}}
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// SDIO SD Card definitions
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// {{{
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wire i_sdcard_ds;
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// }}}
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// Verilator lint_off UNUSED
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wire ign_cpu_stall, ign_cpu_ack;
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wire [31:0] ign_cpu_idata;
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// Verilator lint_on UNUSED
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wire s_clk200;
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wire s_clk, s_reset, sysclk_locked, s_clk_nobuf,
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clk_feedback, clk_feedback_bufd,
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s_lcl_pixclk_nobuf, s_clk4x_unbuffered, s_clk300;
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reg [2:0] pipe_reset;
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reg [6:0] refdly_reset_ctr;
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wire refdly_ready;
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// GPIO declarations. The two wire busses are just virtual lists of
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// input (or output) ports.
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wire [16-1:0] i_gpio;
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wire [8-1:0] o_gpio;
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wire [8-1:0] w_led;
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wire [5-1:0] w_btn;
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//
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// Time to call the main module within main.v. Remember, the purpose
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// of the main.v module is to contain all of our portable logic.
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// Things that are Xilinx (or even Altera) specific, or for that
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// matter anything that requires something other than on-off logic,
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// such as the high impedence states required by many wires, is
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// kept in this (toplevel.v) module. Everything else goes in
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// main.v.
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//
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// We automatically place s_clk, and s_reset here. You may need
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// to define those above. (You did, didn't you?) Other
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// component descriptions come from the keys @TOP.MAIN (if it
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// exists), or @MAIN.PORTLIST if it does not.
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//
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main thedesign(s_clk, s_reset,
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// DDR3 Controller-PHY Interface
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ddr3_controller_iserdes_data, ddr3_controller_iserdes_dqs,
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ddr3_controller_iserdes_bitslip_reference,
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ddr3_controller_idelayctrl_rdy,
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ddr3_controller_cmd,
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ddr3_controller_dqs_tri_control, ddr3_controller_dq_tri_control,
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ddr3_controller_toggle_dqs, ddr3_controller_data, ddr3_controller_dm,
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ddr3_controller_odelay_data_cntvaluein, ddr3_controller_odelay_dqs_cntvaluein,
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ddr3_controller_idelay_data_cntvaluein, ddr3_controller_idelay_dqs_cntvaluein,
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ddr3_controller_odelay_data_ld, ddr3_controller_odelay_dqs_ld,
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ddr3_controller_idelay_data_ld, ddr3_controller_idelay_dqs_ld,
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ddr3_controller_bitslip,
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// Clock Generator ports
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w_sirefclk_word, w_sirefclk_ce,
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// FAN/fan
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i_fan_sda, i_fan_scl,
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o_fan_sda, o_fan_scl,
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o_fan_pwm, o_fan_sys, i_fan_tach,
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// eMMC Card
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o_emmc_clk, i_emmc_ds,
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io_emmc_cmd, io_emmc_dat,
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!i_emmc_cd_n,
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// I2CCPU
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i_i2c_sda, i_i2c_scl,
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o_i2c_sda, o_i2c_scl,
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// SDIO SD Card
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o_sdcard_clk, i_sdcard_ds,
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io_sdcard_cmd, io_sdcard_dat,
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!i_sdcard_cd_n,
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// Reset wire for the ZipCPU
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1'b0, 1'b0, 1'b0, 7'h0, 32'h0,
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ign_cpu_stall, ign_cpu_ack, ign_cpu_idata, s_reset,
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s_clk200,
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// UART/host to wishbone interface
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i_wbu_uart_rx, o_wbu_uart_tx,
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o_wbu_uart_cts_n,
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// GPIO wires
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i_gpio, o_gpio,
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i_sw, w_btn, w_led);
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//
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// Our final section to the toplevel is used to provide all of
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// that special logic that couldnt fit in main. This logic is
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// given by the @TOP.INSERT tag in our data files.
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//
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// DDR3 PHY Instantiation
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ddr3_phy #(
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.ROW_BITS(DDR3_CONTROLLERROW_BITS), //width of row address
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.BA_BITS(DDR3_CONTROLLERBA_BITS), //width of bank address
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.DQ_BITS(DDR3_CONTROLLERDQ_BITS), //width of DQ
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.LANES(DDR3_CONTROLLERLANES), //8 lanes of DQ
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.CONTROLLER_CLK_PERIOD(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD) //ns, period of clock input to DDR3 RAM device
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) ddr3_phy_inst (
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// clock and reset
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.i_controller_clk(s_clk),
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.i_ddr3_clk(s_clk4x),
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.i_ref_clk(s_clk200),
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.i_rst_n(!s_reset),
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// Controller Interface
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.i_controller_cmd(ddr3_controller_cmd),
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.i_controller_dqs_tri_control(ddr3_controller_dqs_tri_control),
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.i_controller_dq_tri_control(ddr3_controller_dq_tri_control),
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.i_controller_toggle_dqs(ddr3_controller_toggle_dqs),
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.i_controller_data(ddr3_controller_data),
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.i_controller_dm(ddr3_controller_dm),
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.i_controller_odelay_data_cntvaluein(ddr3_controller_odelay_data_cntvaluein),
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.i_controller_odelay_dqs_cntvaluein(ddr3_controller_odelay_dqs_cntvaluein),
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.i_controller_idelay_data_cntvaluein(ddr3_controller_idelay_data_cntvaluein),
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.i_controller_idelay_dqs_cntvaluein(ddr3_controller_idelay_dqs_cntvaluein),
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.i_controller_odelay_data_ld(ddr3_controller_odelay_data_ld),
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.i_controller_odelay_dqs_ld(ddr3_controller_odelay_dqs_ld),
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.i_controller_idelay_data_ld(ddr3_controller_idelay_data_ld),
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.i_controller_idelay_dqs_ld(ddr3_controller_idelay_dqs_ld),
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.i_controller_bitslip(ddr3_controller_bitslip),
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.o_controller_iserdes_data(ddr3_controller_iserdes_data),
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.o_controller_iserdes_dqs(ddr3_controller_iserdes_dqs),
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.o_controller_iserdes_bitslip_reference(ddr3_controller_iserdes_bitslip_reference),
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.o_controller_idelayctrl_rdy(ddr3_controller_idelayctrl_rdy),
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// DDR3 I/O Interface
|
|
.o_ddr3_clk_p(o_ddr3_clk_p),
|
|
.o_ddr3_clk_n(o_ddr3_clk_n),
|
|
.o_ddr3_reset_n(o_ddr3_reset_n),
|
|
.o_ddr3_cke(o_ddr3_cke[0]), // CKE
|
|
.o_ddr3_cs_n(o_ddr3_s_n[0]), // chip select signal (controls rank 1 only)
|
|
.o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
|
|
.o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
|
|
.o_ddr3_we_n(o_ddr3_we_n), // WE#
|
|
.o_ddr3_addr(o_ddr3_a[DDR3_CONTROLLERROW_BITS-1:0]),
|
|
.o_ddr3_ba_addr(o_ddr3_ba),
|
|
.io_ddr3_dq(io_ddr3_dq),
|
|
.io_ddr3_dqs(io_ddr3_dqs_p),
|
|
.io_ddr3_dqs_n(io_ddr3_dqs_n),
|
|
.o_ddr3_dm(o_ddr3_dm),
|
|
.o_ddr3_odt(o_ddr3_odt[0]) // on-die termination
|
|
);
|
|
|
|
assign o_ddr3_s_n[1] = 1; // set to 1 (disabled) since controller only supports single rank
|
|
assign o_ddr3_cke[1] = 0; // set to 0 (disabled) since controller only supports single rank
|
|
assign o_ddr3_odt[1] = 0; // set to 0 (disabled) since controller only supports single rank
|
|
generate for(ddr3_controllergen_index = DDR3_CONTROLLERROW_BITS;
|
|
ddr3_controllergen_index < 16;
|
|
ddr3_controllergen_index = ddr3_controllergen_index + 1)
|
|
begin : GEN_UNUSED_DDR3_CONTROLLER_ASSIGN
|
|
assign o_ddr3_a[ddr3_controllergen_index] = 0;
|
|
end endgenerate
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Clock generator for the Si5324
|
|
// {{{
|
|
/*
|
|
PLLE2_BASE #(
|
|
// {{{
|
|
.CLKFBOUT_MULT(8),
|
|
.CLKFBOUT_PHASE(0.0),
|
|
.CLKIN1_PERIOD(10),
|
|
.CLKOUT0_DIVIDE(4),
|
|
.CLKOUT1_DIVIDE(2)
|
|
// }}}
|
|
) gen_sysclk(
|
|
// {{{
|
|
.CLKIN1(i_clk),
|
|
.CLKOUT0(s_clk_200mhz_unbuffered),
|
|
.CLKOUT1(s_clk4x_unbuffered),
|
|
.PWRDWN(1'b0), .RST(1'b0),
|
|
.CLKFBOUT(sysclk_feedback),
|
|
.CLKFBIN(sysclk_feedback),
|
|
.LOCKED(sysclk_locked)
|
|
// }}}
|
|
);
|
|
*/
|
|
// BUFG clksync_buf(.I(s_clksync_unbuffered), .O(s_clk));
|
|
BUFG clk4x_buf(.I(s_clk4x_unbuffered), .O(s_clk4x));
|
|
|
|
xgenclk
|
|
u_xsirefclk(
|
|
// {{{
|
|
.i_clk(s_clk), .i_hsclk(s_clk4x),
|
|
.i_ce(w_sirefclk_ce),
|
|
.i_word(w_sirefclk_word),
|
|
.o_pin({ o_siref_clk_p, o_siref_clk_n }),
|
|
.o_clk(s_sirefclk_clk)
|
|
// }}}
|
|
);
|
|
// }}}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// FAN IO buffers
|
|
// {{{
|
|
|
|
// We need these in order to (properly) ensure the high impedance
|
|
// states (pull ups) of the I2C I/O lines. Our goals are:
|
|
//
|
|
// o_fan_X io_fan_X Derived:T
|
|
// 1'b0 1'b0 1'b0
|
|
// 1'b1 1'bz 1'b1
|
|
//
|
|
IOBUF fansclp(
|
|
// {{{
|
|
.I(1'b0),
|
|
.T(o_fan_scl),
|
|
.O(i_fan_scl),
|
|
.IO(io_temp_scl)
|
|
// }}}
|
|
);
|
|
|
|
IOBUF fansdap(
|
|
// {{{
|
|
.I(1'b0),
|
|
.T(o_fan_sda),
|
|
.O(i_fan_sda),
|
|
.IO(io_temp_sda)
|
|
// }}}
|
|
);
|
|
// }}}
|
|
|
|
assign i_emmc_cd_n = 1'b0;
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// I2C IO buffers
|
|
// {{{
|
|
|
|
// We need these in order to (properly) ensure the high impedance
|
|
// states (pull ups) of the I2C I/O lines. Our goals are:
|
|
//
|
|
// o_i2c_X io_i2c_X Derived:T
|
|
// 1'b0 1'b0 1'b0
|
|
// 1'b1 1'bz 1'b1
|
|
//
|
|
IOBUF i2csclp(
|
|
// {{{
|
|
.I(1'b0),
|
|
.T(o_i2c_scl),
|
|
.O(i_i2c_scl),
|
|
.IO(io_i2c_scl)
|
|
// }}}
|
|
);
|
|
|
|
IOBUF i2csdap(
|
|
// {{{
|
|
.I(1'b0),
|
|
.T(o_i2c_sda),
|
|
.O(i_i2c_sda),
|
|
.IO(io_i2c_sda)
|
|
// }}}
|
|
);
|
|
|
|
initial { r_i2c_mxrst_n, r_i2c_mxrst_dly } = 0;
|
|
always @(posedge s_clk or negedge sysclk_locked)
|
|
if (!sysclk_locked)
|
|
{ r_i2c_mxrst_n, r_i2c_mxrst_dly } <= 0;
|
|
else
|
|
{ r_i2c_mxrst_n, r_i2c_mxrst_dly } <= { r_i2c_mxrst_dly, 1'b1 };
|
|
|
|
assign o_i2c_mxrst_n = r_i2c_mxrst_n;
|
|
// }}}
|
|
|
|
assign i_sdcard_ds = 1'b0;
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// 200MHz clock ingestion
|
|
// {{{
|
|
IBUFDS
|
|
ibuf_ck200 (
|
|
.I(i_clk_200mhz_p), .IB(i_clk_200mhz_n),
|
|
.O(s_clk200)
|
|
);
|
|
// }}}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Default clock setup
|
|
// {{{
|
|
// assign s_clk=s_clk200;
|
|
// assign sysclk_locked = 1'b1;
|
|
|
|
initial pipe_reset = -1;
|
|
always @(posedge s_clk or negedge sysclk_locked)
|
|
if (!sysclk_locked)
|
|
pipe_reset <= -1;
|
|
else
|
|
pipe_reset <= { pipe_reset[1:0], 1'b0 };
|
|
|
|
assign s_reset = pipe_reset[2];
|
|
|
|
PLLE2_BASE #(
|
|
.CLKFBOUT_MULT(6), // 200MHz*6 => 1200MHz
|
|
.CLKFBOUT_PHASE(0.0),
|
|
.CLKIN1_PERIOD(5),
|
|
.CLKOUT0_DIVIDE(12), // Divide by 2x
|
|
.CLKOUT1_DIVIDE(3), // Multiply by 2x
|
|
.CLKOUT2_DIVIDE(30), // Divide by 5x
|
|
.CLKOUT3_DIVIDE(4) // Multiply by 3/2
|
|
) u_syspll (
|
|
.CLKOUT0(s_clk_nobuf), // 100MHz
|
|
.CLKOUT1(s_clk4x_unbuffered), // 400MHz
|
|
.CLKOUT2(s_lcl_pixclk_nobuf), // 40MHz
|
|
.CLKOUT3(s_clk300), // 300MHz
|
|
//
|
|
.CLKFBOUT(clk_feedback),
|
|
.LOCKED(sysclk_locked),
|
|
.CLKIN1(s_clk200), // 200MHz
|
|
.PWRDWN(1'b0),
|
|
.CLKFBIN(clk_feedback_bufd)
|
|
);
|
|
|
|
BUFG feedback_buffer(.I(clk_feedback), .O(clk_feedback_bufd));
|
|
BUFG sysclk_buffer(.I(s_clk_nobuf), .O(s_clk));
|
|
// BUFG sysclk_buffer(.I(s_lcl_pixclk_nobuf), .O(s_lcl_pixclk));
|
|
|
|
// IDELAYCTRL
|
|
// {{{
|
|
// Min reset width of 52ns, or 9 clocks at 150MHz
|
|
always @(posedge s_clk300 or negedge sysclk_locked)
|
|
if (!sysclk_locked)
|
|
refdly_reset_ctr <= 0;
|
|
else if (!refdly_reset_ctr[5])
|
|
refdly_reset_ctr <= refdly_reset_ctr + 1;
|
|
|
|
IDELAYCTRL
|
|
u_dlyctrl (.REFCLK(s_clk300), .RST(refdly_reset_ctr[5]),
|
|
.RDY(refdly_ready));
|
|
// }}}
|
|
// }}}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// GPIO adjustments
|
|
// {{{
|
|
// Set to '1' when there's something to say. Hence, the reset
|
|
// inputs will be '1' when the reset is active, the HDMI detect
|
|
// will be '1' when an HDMI is detected, the PLL lock signals
|
|
// will be '1' when not locked, etc.
|
|
assign i_gpio = { 11'h0,
|
|
1'b0, // Was pxrx_locked
|
|
!i_hdmitx_hpd_n,
|
|
i_si5324_int,!sysclk_locked,!i_pi_reset_n,i_soft_reset };
|
|
assign o_tp = o_gpio[3:0];
|
|
assign o_si5324_rst = o_gpio[4];
|
|
assign o_hdmirx_hpd_n = o_gpio[5];
|
|
// o_trace = o_gpio[6]; // But this is for simulation only, so ignore
|
|
// o_error = o_gpio[7]; // SIM ONLY: Internal error detection
|
|
// }}}
|
|
|
|
assign o_led = { w_led[8-1:2], (w_led[1] || !sysclk_locked),
|
|
w_led[0] | s_reset };
|
|
|
|
assign w_btn = ~{ i_nbtn_u, i_nbtn_l, i_nbtn_c, i_nbtn_r, i_nbtn_d };
|
|
|
|
|
|
|
|
endmodule // end of toplevel.v module definition
|