129 lines
3.4 KiB
Verilog
129 lines
3.4 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: smitest.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, files
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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`default_nettype none
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// }}}
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module smitest (
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input wire i_clk_200mhz_p, i_clk_200mhz_n,
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input wire i_wbu_uart_rx,
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output wire o_wbu_uart_tx,
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output wire o_wbu_uart_cts_n,
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input wire i_smi_wen, i_smi_oen,
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input wire [5:0] i_smi_sa,
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inout wire [17:0] io_smi_sd
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);
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localparam real CLOCK_FREQUENCY_MHZ = 200.0,
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BAUD_RATE_KHZ = 19.200;
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localparam CLOCKS_PER_BAUD = $rtoi(CLOCK_FREQUENCY_MHZ * 1000.0
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/ BAUD_RATE_KHZ),
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TIMING_BITS = $clog2(CLOCKS_PER_BAUD+1);
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wire ck_prebuf, s_clk;
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wire rx_valid, rx_ready, tx_valid, tx_ready, tx_busy;
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wire [7:0] rx_data, tx_data;
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wire [17:0] o_smi_data;
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wire o_smi_oen;
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reg s_reset;
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reg [1:0] reset_pipe;
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IBUFDS
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clk_ibuf (
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.I(i_clk_200mhz_p), .IB(i_clk_200mhz_n),
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.O(ck_prebuf)
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);
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BUFG clk_bfg ( .I(ck_prebuf), .O(s_clk) );
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initial { s_reset, reset_pipe } = -1;
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always @(posedge s_clk)
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{ s_reset, reset_pipe } <= { reset_pipe, 1'b0 };
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txuartlite #(
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.TIMING_BITS(TIMING_BITS[4:0]),
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.CLOCKS_PER_BAUD(CLOCKS_PER_BAUD[TIMING_BITS-1:0])
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) u_txuart (
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.i_clk(s_clk), .i_wr(tx_valid && !tx_busy),
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.i_data(tx_data),
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.o_uart_tx(o_wbu_uart_tx), .o_busy(tx_busy)
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);
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assign tx_ready = !tx_busy;
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rxuartlite #(
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.TIMER_BITS(TIMING_BITS[4:0]),
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.CLOCKS_PER_BAUD(CLOCKS_PER_BAUD[TIMING_BITS-1:0])
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) u_rxuart (
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.i_clk(s_clk), .i_uart_rx(i_wbu_uart_rx),
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.o_wr(rx_valid), .o_data(rx_data)
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);
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assign o_wbu_uart_cts_n = o_smi_data[8];
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smi #(
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.OPT_ASYNC(1'b0)
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) u_smi (
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.i_clk(s_clk), .i_reset(s_reset),
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.i_smi_oen(i_smi_oen), .i_smi_wen(i_smi_wen),
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.i_smi_sa(i_smi_sa),
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.i_smi_data(io_smi_sd), .o_smi_data(o_smi_data),
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.o_smi_oen(o_smi_oen),
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.S_TX_VALID(rx_valid), .S_TX_READY(rx_ready),
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.S_TX_DATA(rx_data),
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.M_RX_VALID(tx_valid), .M_RX_READY(tx_ready),
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.M_RX_DATA(tx_data)
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);
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assign io_smi_sd = (o_smi_oen) ? 18'hz : o_smi_data;
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// Verilator lint_off UNUSED
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wire unused;
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assign unused = &{ 1'b0, rx_ready };
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// Verilator lint_on UNUSED
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endmodule
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`ifdef VERILATOR
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// {{{
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// Verilator lint_off DECLFILENAME
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module IBUFDS ( input wire I, input wire IB, output wire O );
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assign O = I;
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// Verilator lint_off UNUSED
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wire unused = IB;
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// Verilator lint_on UNUSED
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endmodule
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module BUFG ( input wire I, output wire O );
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assign O = I;
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endmodule
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// Verilator lint_on DECLFILENAME
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// }}}
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`endif // VERILATOR
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