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UberDDR3/delete_later/rtl/main.v

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`timescale 1ps / 1ps
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ./main.v
// {{{
// Project: 10Gb Ethernet switch
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: autofpga autofpga -I .: -d -o . allclocks.txt global.txt wbdown.txt icape.txt version.txt gpio.txt spio.txt wbuconsole.txt zipmaster.txt bkram.txt ddr3.txt sdio.txt emmc.txt sdioscope.txt emmcscope.txt mem_bkram_only.txt mem_flash_bkram.txt i2ccpu.txt fan.txt sirefclk.txt i2cscope.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2023, Gisselquist Technology, LLC
// {{{
// This file is part of the ETH10G project.
//
// The ETH10G project contains free software and gateware, licensed under the
// Apache License, Version 2.0 (the "License"). You may not use this project,
// or this file, except in compliance with the License. You may obtain a copy
// of the License at
// }}}
// http://www.apache.org/licenses/LICENSE-2.0
// {{{
// Unless required by applicable law or agreed to in writing, files
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
`default_nettype none
////////////////////////////////////////////////////////////////////////////////
//
// Macro defines
// {{{
//
//
// Here is a list of defines which may be used, post auto-design
// (not post-build), to turn particular peripherals (and bus masters)
// on and off. In particular, to turn off support for a particular
// design component, just comment out its respective `define below.
//
// These lines are taken from the respective @ACCESS tags for each of our
// components. If a component doesn't have an @ACCESS tag, it will not
// be listed here.
//
// First, the independent access fields for any bus masters
`define WBUBUS_MASTER
// And then for the independent peripherals
`define EMMCSCOPE_SCOPC
`define SDIOSCOPE_SCOPC
`define DDR3_CONTROLLER_ACCESS
`define BKRAM_ACCESS
`define SIREFCLK_ACCESS
`define I2CDMA_ACCESS
`define DDR3_PHY_ACCESS
`define FAN_ACCESS
`define EMMC_ACCESS
`define I2CCPU_ACCESS
`define SDIO_ACCESS
`define BUSCONSOLE_ACCESS
`define INCLUDE_ZIPCPU
`define VERSION_ACCESS
`define I2CSCOPE_SCOPC
`define CFG_ACCESS
`define GPIO_ACCESS
`define SPIO_ACCESS
//
// End of dependency list
//
//
// }}}
////////////////////////////////////////////////////////////////////////////////
//
// Any include files
// {{{
// These are drawn from anything with a MAIN.INCLUDE definition.
`define INCLUDE_DMA_CONTROLLER
`define INCLUDE_ACCOUNTING_COUNTERS
`include "builddate.v"
// }}}
//
// Finally, we define our main module itself. We start with the list of
// I/O ports, or wires, passed into (or out of) the main function.
//
// These fields are copied verbatim from the respective I/O port lists,
// from the fields given by @MAIN.PORTLIST
//
module main(i_clk, i_reset,
// {{{
// DDR3 Controller Interface
i_ddr3_controller_iserdes_data, i_ddr3_controller_iserdes_dqs,
i_ddr3_controller_iserdes_bitslip_reference,
i_ddr3_controller_idelayctrl_rdy,
o_ddr3_controller_cmd,
o_ddr3_controller_dqs_tri_control, o_ddr3_controller_dq_tri_control,
o_ddr3_controller_toggle_dqs, o_ddr3_controller_data, o_ddr3_controller_dm,
o_ddr3_controller_odelay_data_cntvaluein, o_ddr3_controller_odelay_dqs_cntvaluein,
o_ddr3_controller_idelay_data_cntvaluein, o_ddr3_controller_idelay_dqs_cntvaluein,
o_ddr3_controller_odelay_data_ld, o_ddr3_controller_odelay_dqs_ld,
o_ddr3_controller_idelay_data_ld, o_ddr3_controller_idelay_dqs_ld,
o_ddr3_controller_bitslip,
// Clock generator ports
o_sirefclk_word, o_sirefclk_ce,
i_fan_sda, i_fan_scl,
o_fan_sda, o_fan_scl,
o_fpga_pwm, o_sys_pwm, i_fan_tach,
// eMMC Card
o_emmc_clk, i_emmc_ds,
`ifdef VERILATOR
io_emmc_cmd_tristate,
o_emmc_cmd, i_emmc_cmd,
io_emmc_dat_tristate,
o_emmc_dat, i_emmc_dat,
`else
io_emmc_cmd, io_emmc_dat,
`endif
i_emmc_detect,
i_i2c_sda, i_i2c_scl,
o_i2c_sda, o_i2c_scl,
// SDIO SD Card
o_sdcard_clk, i_sdcard_ds,
`ifdef VERILATOR
io_sdcard_cmd_tristate,
o_sdcard_cmd, i_sdcard_cmd,
io_sdcard_dat_tristate,
o_sdcard_dat, i_sdcard_dat,
`else
io_sdcard_cmd, io_sdcard_dat,
`endif
i_sdcard_detect,
// Veri1ator only interface
cpu_sim_cyc,
cpu_sim_stb,
cpu_sim_we,
cpu_sim_addr,
cpu_sim_data,
cpu_sim_stall,
cpu_sim_ack,
cpu_sim_idata,
`ifdef VERILATOR
cpu_prof_stb,
cpu_prof_addr,
cpu_prof_ticks,
`endif
i_cpu_reset,
i_clk200,
// UART/host to wishbone interface
i_wbu_uart_rx, o_wbu_uart_tx,
o_wbu_uart_cts_n,
// GPIO ports
i_gpio, o_gpio,
// SPIO interface
i_sw, i_btn, o_led
// }}}
);
////////////////////////////////////////////////////////////////////////////////
//
// Any parameter definitions
// {{{
// These are drawn from anything with a MAIN.PARAM definition.
// As they aren't connected to the toplevel at all, it would
// be best to use localparam over parameter, but here we don't
// check
localparam real DDR3_CONTROLLERCONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device
localparam DDR3_CONTROLLERROW_BITS = 14, // width of row address
DDR3_CONTROLLERCOL_BITS = 10, // width of column address
DDR3_CONTROLLERBA_BITS = 3, // width of bank address
DDR3_CONTROLLERDQ_BITS = 8, // Size of one octet
DDR3_CONTROLLERLANES = 8, //8 lanes of DQ
DDR3_CONTROLLERAUX_WIDTH = 1,
DDR3_CONTROLLERSERDES_RATIO = $rtoi(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
//4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
DDR3_CONTROLLERCMD_LEN = 4 + 3 + DDR3_CONTROLLERBA_BITS + DDR3_CONTROLLERROW_BITS;
////////////////////////////////////////////////////////////////////////
//
// Variables/definitions/parameters used by the ZipCPU bus master
// {{{
//
// A 32-bit address indicating where the ZipCPU should start running
// from
`ifdef BKROM_ACCESS
localparam RESET_ADDRESS = @$(/bkrom.BASE);
`else
`ifdef FLASH_ACCESS
localparam RESET_ADDRESS = @$RESET_ADDRESS;
`else
localparam RESET_ADDRESS = 67108864;
`endif // FLASH_ACCESS
`endif // BKROM_ACCESS
//
// The number of valid bits on the bus
localparam ZIP_ADDRESS_WIDTH = 22; // Zip-CPU address width
//
// Number of ZipCPU interrupts
localparam ZIP_INTS = 16;
//
// ZIP_START_HALTED
//
// A boolean, indicating whether or not the ZipCPU be halted on startup?
`ifdef BKROM_ACCESS
localparam ZIP_START_HALTED=1'b0;
`else
localparam ZIP_START_HALTED=1'b1;
`endif
// }}}
////////////////////////////////////////////////////////////////////////
//
// WBUBUS parameters
// {{{
// Baudrate : 1000000
// Clock : 100000000
localparam [23:0] BUSUART = 24'h64; // 1000000 baud
localparam DBGBUSBITS = $clog2(BUSUART);
//
// Maximum command is 6 bytes, where each byte takes 10 baud clocks
// and each baud clock requires DBGBUSBITS to represent. Here,
// we'll add one more for good measure.
localparam DBGBUSWATCHDOG_RAW = DBGBUSBITS + 9;
localparam DBGBUSWATCHDOG = (DBGBUSWATCHDOG_RAW > 19)
? DBGBUSWATCHDOG_RAW : 19;
// }}}
localparam ICAPE_LGDIV=3;
// }}}
////////////////////////////////////////////////////////////////////////////////
//
// Port declarations
// {{{
// The next step is to declare all of the various ports that were just
// listed above.
//
// The following declarations are taken from the values of the various
// @MAIN.IODECL keys.
//
input wire i_clk;
// verilator lint_off UNUSED
input wire i_reset;
// verilator lint_on UNUSED
// DDR3 Controller I/O declarations
// {{{
input wire [DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES*8-1:0] i_ddr3_controller_iserdes_data;
input wire [DDR3_CONTROLLERLANES*8-1:0] i_ddr3_controller_iserdes_dqs;
input wire [DDR3_CONTROLLERLANES*8-1:0] i_ddr3_controller_iserdes_bitslip_reference;
input wire i_ddr3_controller_idelayctrl_rdy;
output wire [DDR3_CONTROLLERCMD_LEN*DDR3_CONTROLLERSERDES_RATIO-1:0] o_ddr3_controller_cmd;
output wire o_ddr3_controller_dqs_tri_control, o_ddr3_controller_dq_tri_control;
output wire o_ddr3_controller_toggle_dqs;
output wire [512-1:0] o_ddr3_controller_data;
output wire [512/8-1:0] o_ddr3_controller_dm;
output wire [4:0] o_ddr3_controller_odelay_data_cntvaluein, o_ddr3_controller_odelay_dqs_cntvaluein;
output wire [4:0] o_ddr3_controller_idelay_data_cntvaluein, o_ddr3_controller_idelay_dqs_cntvaluein;
output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_controller_odelay_data_ld, o_ddr3_controller_odelay_dqs_ld;
output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_controller_idelay_data_ld, o_ddr3_controller_idelay_dqs_ld;
output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_controller_bitslip;
// }}}
output wire [7:0] o_sirefclk_word;
output wire o_sirefclk_ce;
// FAN Port declarations
// {{{
input wire i_fan_sda, i_fan_scl;
output wire o_fan_sda, o_fan_scl;
output wire o_fpga_pwm, o_sys_pwm;
input wire i_fan_tach;
// }}}
// eMMC Card declarations
// {{{
output wire o_emmc_clk;
input wire i_emmc_ds;
`ifdef VERILATOR
output wire io_emmc_cmd_tristate;
output wire o_emmc_cmd;
input wire i_emmc_cmd;
output wire [8-1:0] io_emmc_dat_tristate;
output wire [8-1:0] o_emmc_dat;
input wire [8-1:0] i_emmc_dat;
`else
inout wire io_emmc_cmd;
inout wire [8-1:0] io_emmc_dat;
`endif
input wire i_emmc_detect;
// }}}
// I2C Port declarations
// {{{
input wire i_i2c_sda, i_i2c_scl;
output wire o_i2c_sda, o_i2c_scl;
// }}}
// SDIO SD Card declarations
// {{{
output wire o_sdcard_clk;
input wire i_sdcard_ds;
`ifdef VERILATOR
output wire io_sdcard_cmd_tristate;
output wire o_sdcard_cmd;
input wire i_sdcard_cmd;
output wire [4-1:0] io_sdcard_dat_tristate;
output wire [4-1:0] o_sdcard_dat;
input wire [4-1:0] i_sdcard_dat;
`else
inout wire io_sdcard_cmd;
inout wire [4-1:0] io_sdcard_dat;
`endif
input wire i_sdcard_detect;
// }}}
input wire cpu_sim_cyc, cpu_sim_stb;
input wire cpu_sim_we;
input wire [6:0] cpu_sim_addr;
input wire [31:0] cpu_sim_data;
//
output wire cpu_sim_stall, cpu_sim_ack;
output wire [31:0] cpu_sim_idata;
//
`ifdef VERILATOR
output wire cpu_prof_stb;
output wire [22+$clog2(512/8)-1:0] cpu_prof_addr;
output wire [31:0] cpu_prof_ticks;
`endif
input wire i_cpu_reset;
input wire i_wbu_uart_rx;
output wire o_wbu_uart_tx;
// input wire i_wbu_uart_rts_n; // FT*'s perspective
output wire o_wbu_uart_cts_n;
localparam NGPI = 16, NGPO=8;
// GPIO ports
input [(NGPI-1):0] i_gpio;
output wire [(NGPO-1):0] o_gpio;
// SPIO interface
input wire [8-1:0] i_sw;
input wire [5-1:0] i_btn;
output wire [8-1:0] o_led;
// }}}
// Make Verilator happy
// {{{
// Defining bus wires for lots of components often ends up with unused
// wires lying around. We'll turn off Ver1lator's lint warning
// here that checks for unused wires.
// }}}
// verilator lint_off UNUSED
////////////////////////////////////////////////////////////////////////
//
// Declaring interrupt lines
// {{{
// These declarations come from the various components values
// given under the @INT.<interrupt name>.WIRE key.
//
wire emmcscope_int; // emmcscope.INT.EMMCSCOPE.WIRE
wire sdioscope_int; // sdioscope.INT.SDIOSCOPE.WIRE
wire emmc_int; // emmc.INT.EMMC.WIRE
wire sdcard_int; // sdcard.INT.SDCARD.WIRE
wire uartrxf_int; // uart.INT.UARTRXF.WIRE
wire uarttx_int; // uart.INT.UARTTX.WIRE
wire uarttxf_int; // uart.INT.UARTTXF.WIRE
wire uartrx_int; // uart.INT.UARTRX.WIRE
wire i2cscope_int; // i2cscope.INT.I2CSCOPE.WIRE
wire gpio_int; // gpio.INT.GPIO.WIRE
wire spio_int; // spio.INT.SPIO.WIRE
// }}}
////////////////////////////////////////////////////////////////////////
//
// Component declarations
// {{{
// These declarations come from the @MAIN.DEFNS keys found in the
// various components comprising the design.
//
// Verilator lint_off UNUSED
wire [DDR3_CONTROLLERAUX_WIDTH-1:0] ddr3_controller_aux_out;
// Verilator lint_on UNUSED
reg r_sirefclk_en;
reg [29:0] r_sirefclk_data;
wire w_sirefclk_unused_stb;
reg r_sirefclk_ack;
wire i2cdma_ready;
// FAN/fan Controller
// {{{
// Verilator lint_off UNUSED
wire [31:0] fan_debug;
// Verilator lint_on UNUSED
// }}}
// eMMC Card definitions
// Verilator lint_off UNUSED
wire w_emmc_1p8v;
wire [31:0] emmc_debug;
// Verilator lint_on UNUSED
// I2C Controller
// {{{
// Verilator lint_off UNUSED
localparam I2C_ID_WIDTH=(2 == 0) ? 1 : 2;
wire i2c_valid, i2c_ready, i2c_last;
wire [7:0] i2c_data;
wire [I2C_ID_WIDTH-1:0] i2c_id;
wire [31:0] i2c_debug;
// Verilator lint_on UNUSED
// }}}
// SDIO SD Card definitions
// Verilator lint_off UNUSED
wire w_sdcard_1p8v;
wire [31:0] sdcard_debug;
// Verilator lint_on UNUSED
// BUILDTIME doesnt need to include builddate.v a second time
// `include "builddate.v"
////////////////////////////////////////////////////////////////////////
//
// WBUBUS: Console definitions
// {{{
wire w_console_rx_stb, w_console_tx_stb, w_console_busy;
wire [6:0] w_console_rx_data, w_console_tx_data;
// Verilator lint_off UNUSED
wire [31:0] uart_debug;
// Verilator lint_on UNUSED
// }}}
////////////////////////////////////////////////////////////////////////
//
// ZipSystem/ZipCPU connection definitions
// {{{
`ifndef VERILATOR
wire cpu_prof_stb;
wire [22+$clog2(512/8)-1:0] cpu_prof_addr;
wire [31:0] cpu_prof_ticks;
`endif
// All we define here is a set of scope wires
// Verilator lint_off UNUSED
wire raw_cpu_dbg_stall, raw_cpu_dbg_ack;
wire [31:0] zip_debug;
wire zip_trigger;
// Verilator lint_on UNUSED
wire [ZIP_INTS-1:0] zip_int_vector;
wire zip_cpu_int;
// }}}
// Verilator lint_off UNUSED
input wire i_clk200;
// Verilator lint_on UNUSED
////////////////////////////////////////////////////////////////////////
//
// WBUBUS: USB-UART interface declarations
// {{{
//
wire [7:0] wbu_rx_data, wbu_tx_data;
wire wbu_rx_stb;
wire wbu_tx_stb, wbu_tx_busy;
// Definitions for the WB-UART converter. We really only need one
// (more) non-bus wire--one to use to select if we are interacting
// with the ZipCPU or not.
// Verilator lint_off UNUSED
wire [0:0] wbubus_dbg;
// Verilator lint_on UNUSED
// }}}
// Verilator lint_off UNUSED
wire [31:0] cfg_debug;
// Verilator lint_on UNUSED
wire [8-1:0] w_led;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Declaring interrupt vector wires
// {{{
// These declarations come from the various components having
// PIC and PIC.MAX keys.
//
wire [14:0] sys_int_vector;
wire [14:0] alt_int_vector;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Declare bus signals
// {{{
////////////////////////////////////////////////////////////////////////
// Bus wbwide
// {{{
// Wishbone definitions for bus wbwide, component i2cdma
// Verilator lint_off UNUSED
wire wbwide_i2cdma_cyc, wbwide_i2cdma_stb, wbwide_i2cdma_we;
wire [21:0] wbwide_i2cdma_addr;
wire [511:0] wbwide_i2cdma_data;
wire [63:0] wbwide_i2cdma_sel;
wire wbwide_i2cdma_stall, wbwide_i2cdma_ack, wbwide_i2cdma_err;
wire [511:0] wbwide_i2cdma_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbwide, component i2c
// Verilator lint_off UNUSED
wire wbwide_i2cm_cyc, wbwide_i2cm_stb, wbwide_i2cm_we;
wire [21:0] wbwide_i2cm_addr;
wire [511:0] wbwide_i2cm_data;
wire [63:0] wbwide_i2cm_sel;
wire wbwide_i2cm_stall, wbwide_i2cm_ack, wbwide_i2cm_err;
wire [511:0] wbwide_i2cm_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbwide, component zip
// Verilator lint_off UNUSED
wire wbwide_zip_cyc, wbwide_zip_stb, wbwide_zip_we;
wire [21:0] wbwide_zip_addr;
wire [511:0] wbwide_zip_data;
wire [63:0] wbwide_zip_sel;
wire wbwide_zip_stall, wbwide_zip_ack, wbwide_zip_err;
wire [511:0] wbwide_zip_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbwide, component wbu_arbiter
// Verilator lint_off UNUSED
wire wbwide_wbu_arbiter_cyc, wbwide_wbu_arbiter_stb, wbwide_wbu_arbiter_we;
wire [21:0] wbwide_wbu_arbiter_addr;
wire [511:0] wbwide_wbu_arbiter_data;
wire [63:0] wbwide_wbu_arbiter_sel;
wire wbwide_wbu_arbiter_stall, wbwide_wbu_arbiter_ack, wbwide_wbu_arbiter_err;
wire [511:0] wbwide_wbu_arbiter_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbwide, component wbdown
// Verilator lint_off UNUSED
wire wbwide_wbdown_cyc, wbwide_wbdown_stb, wbwide_wbdown_we;
wire [21:0] wbwide_wbdown_addr;
wire [511:0] wbwide_wbdown_data;
wire [63:0] wbwide_wbdown_sel;
wire wbwide_wbdown_stall, wbwide_wbdown_ack, wbwide_wbdown_err;
wire [511:0] wbwide_wbdown_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbwide, component bkram
// Verilator lint_off UNUSED
wire wbwide_bkram_cyc, wbwide_bkram_stb, wbwide_bkram_we;
wire [21:0] wbwide_bkram_addr;
wire [511:0] wbwide_bkram_data;
wire [63:0] wbwide_bkram_sel;
wire wbwide_bkram_stall, wbwide_bkram_ack, wbwide_bkram_err;
wire [511:0] wbwide_bkram_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbwide, component ddr3_controller
// Verilator lint_off UNUSED
wire wbwide_ddr3_controller_cyc, wbwide_ddr3_controller_stb, wbwide_ddr3_controller_we;
wire [21:0] wbwide_ddr3_controller_addr;
wire [511:0] wbwide_ddr3_controller_data;
wire [63:0] wbwide_ddr3_controller_sel;
wire wbwide_ddr3_controller_stall, wbwide_ddr3_controller_ack, wbwide_ddr3_controller_err;
wire [511:0] wbwide_ddr3_controller_idata;
// Verilator lint_on UNUSED
// }}}
// Bus wb32
// {{{
// Wishbone definitions for bus wb32, component wbdown
// Verilator lint_off UNUSED
wire wb32_wbdown_cyc, wb32_wbdown_stb, wb32_wbdown_we;
wire [7:0] wb32_wbdown_addr;
wire [31:0] wb32_wbdown_data;
wire [3:0] wb32_wbdown_sel;
wire wb32_wbdown_stall, wb32_wbdown_ack, wb32_wbdown_err;
wire [31:0] wb32_wbdown_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32(SIO), component buildtime
// Verilator lint_off UNUSED
wire wb32_buildtime_cyc, wb32_buildtime_stb, wb32_buildtime_we;
wire [7:0] wb32_buildtime_addr;
wire [31:0] wb32_buildtime_data;
wire [3:0] wb32_buildtime_sel;
wire wb32_buildtime_stall, wb32_buildtime_ack, wb32_buildtime_err;
wire [31:0] wb32_buildtime_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32(SIO), component gpio
// Verilator lint_off UNUSED
wire wb32_gpio_cyc, wb32_gpio_stb, wb32_gpio_we;
wire [7:0] wb32_gpio_addr;
wire [31:0] wb32_gpio_data;
wire [3:0] wb32_gpio_sel;
wire wb32_gpio_stall, wb32_gpio_ack, wb32_gpio_err;
wire [31:0] wb32_gpio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32(SIO), component sirefclk
// Verilator lint_off UNUSED
wire wb32_sirefclk_cyc, wb32_sirefclk_stb, wb32_sirefclk_we;
wire [7:0] wb32_sirefclk_addr;
wire [31:0] wb32_sirefclk_data;
wire [3:0] wb32_sirefclk_sel;
wire wb32_sirefclk_stall, wb32_sirefclk_ack, wb32_sirefclk_err;
wire [31:0] wb32_sirefclk_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32(SIO), component spio
// Verilator lint_off UNUSED
wire wb32_spio_cyc, wb32_spio_stb, wb32_spio_we;
wire [7:0] wb32_spio_addr;
wire [31:0] wb32_spio_data;
wire [3:0] wb32_spio_sel;
wire wb32_spio_stall, wb32_spio_ack, wb32_spio_err;
wire [31:0] wb32_spio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32(SIO), component version
// Verilator lint_off UNUSED
wire wb32_version_cyc, wb32_version_stb, wb32_version_we;
wire [7:0] wb32_version_addr;
wire [31:0] wb32_version_data;
wire [3:0] wb32_version_sel;
wire wb32_version_stall, wb32_version_ack, wb32_version_err;
wire [31:0] wb32_version_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component emmcscope
// Verilator lint_off UNUSED
wire wb32_emmcscope_cyc, wb32_emmcscope_stb, wb32_emmcscope_we;
wire [7:0] wb32_emmcscope_addr;
wire [31:0] wb32_emmcscope_data;
wire [3:0] wb32_emmcscope_sel;
wire wb32_emmcscope_stall, wb32_emmcscope_ack, wb32_emmcscope_err;
wire [31:0] wb32_emmcscope_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component i2cscope
// Verilator lint_off UNUSED
wire wb32_i2cscope_cyc, wb32_i2cscope_stb, wb32_i2cscope_we;
wire [7:0] wb32_i2cscope_addr;
wire [31:0] wb32_i2cscope_data;
wire [3:0] wb32_i2cscope_sel;
wire wb32_i2cscope_stall, wb32_i2cscope_ack, wb32_i2cscope_err;
wire [31:0] wb32_i2cscope_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component sdioscope
// Verilator lint_off UNUSED
wire wb32_sdioscope_cyc, wb32_sdioscope_stb, wb32_sdioscope_we;
wire [7:0] wb32_sdioscope_addr;
wire [31:0] wb32_sdioscope_data;
wire [3:0] wb32_sdioscope_sel;
wire wb32_sdioscope_stall, wb32_sdioscope_ack, wb32_sdioscope_err;
wire [31:0] wb32_sdioscope_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component i2c
// Verilator lint_off UNUSED
wire wb32_i2cs_cyc, wb32_i2cs_stb, wb32_i2cs_we;
wire [7:0] wb32_i2cs_addr;
wire [31:0] wb32_i2cs_data;
wire [3:0] wb32_i2cs_sel;
wire wb32_i2cs_stall, wb32_i2cs_ack, wb32_i2cs_err;
wire [31:0] wb32_i2cs_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component i2cdma
// Verilator lint_off UNUSED
wire wb32_i2cdma_cyc, wb32_i2cdma_stb, wb32_i2cdma_we;
wire [7:0] wb32_i2cdma_addr;
wire [31:0] wb32_i2cdma_data;
wire [3:0] wb32_i2cdma_sel;
wire wb32_i2cdma_stall, wb32_i2cdma_ack, wb32_i2cdma_err;
wire [31:0] wb32_i2cdma_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component uart
// Verilator lint_off UNUSED
wire wb32_uart_cyc, wb32_uart_stb, wb32_uart_we;
wire [7:0] wb32_uart_addr;
wire [31:0] wb32_uart_data;
wire [3:0] wb32_uart_sel;
wire wb32_uart_stall, wb32_uart_ack, wb32_uart_err;
wire [31:0] wb32_uart_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component emmc
// Verilator lint_off UNUSED
wire wb32_emmc_cyc, wb32_emmc_stb, wb32_emmc_we;
wire [7:0] wb32_emmc_addr;
wire [31:0] wb32_emmc_data;
wire [3:0] wb32_emmc_sel;
wire wb32_emmc_stall, wb32_emmc_ack, wb32_emmc_err;
wire [31:0] wb32_emmc_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component fan
// Verilator lint_off UNUSED
wire wb32_fan_cyc, wb32_fan_stb, wb32_fan_we;
wire [7:0] wb32_fan_addr;
wire [31:0] wb32_fan_data;
wire [3:0] wb32_fan_sel;
wire wb32_fan_stall, wb32_fan_ack, wb32_fan_err;
wire [31:0] wb32_fan_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component sdcard
// Verilator lint_off UNUSED
wire wb32_sdcard_cyc, wb32_sdcard_stb, wb32_sdcard_we;
wire [7:0] wb32_sdcard_addr;
wire [31:0] wb32_sdcard_data;
wire [3:0] wb32_sdcard_sel;
wire wb32_sdcard_stall, wb32_sdcard_ack, wb32_sdcard_err;
wire [31:0] wb32_sdcard_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component wb32_sio
// Verilator lint_off UNUSED
wire wb32_sio_cyc, wb32_sio_stb, wb32_sio_we;
wire [7:0] wb32_sio_addr;
wire [31:0] wb32_sio_data;
wire [3:0] wb32_sio_sel;
wire wb32_sio_stall, wb32_sio_ack, wb32_sio_err;
wire [31:0] wb32_sio_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component cfg
// Verilator lint_off UNUSED
wire wb32_cfg_cyc, wb32_cfg_stb, wb32_cfg_we;
wire [7:0] wb32_cfg_addr;
wire [31:0] wb32_cfg_data;
wire [3:0] wb32_cfg_sel;
wire wb32_cfg_stall, wb32_cfg_ack, wb32_cfg_err;
wire [31:0] wb32_cfg_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wb32, component ddr3_phy
// Verilator lint_off UNUSED
wire wb32_ddr3_phy_cyc, wb32_ddr3_phy_stb, wb32_ddr3_phy_we;
wire [7:0] wb32_ddr3_phy_addr;
wire [31:0] wb32_ddr3_phy_data;
wire [3:0] wb32_ddr3_phy_sel;
wire wb32_ddr3_phy_stall, wb32_ddr3_phy_ack, wb32_ddr3_phy_err;
wire [31:0] wb32_ddr3_phy_idata;
// Verilator lint_on UNUSED
// }}}
// Bus wbu
// {{{
// Wishbone definitions for bus wbu, component wbu
// Verilator lint_off UNUSED
wire wbu_cyc, wbu_stb, wbu_we;
wire [26:0] wbu_addr;
wire [31:0] wbu_data;
wire [3:0] wbu_sel;
wire wbu_stall, wbu_ack, wbu_err;
wire [31:0] wbu_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbu, component wbu_arbiter
// Verilator lint_off UNUSED
wire wbu_wbu_arbiter_cyc, wbu_wbu_arbiter_stb, wbu_wbu_arbiter_we;
wire [26:0] wbu_wbu_arbiter_addr;
wire [31:0] wbu_wbu_arbiter_data;
wire [3:0] wbu_wbu_arbiter_sel;
wire wbu_wbu_arbiter_stall, wbu_wbu_arbiter_ack, wbu_wbu_arbiter_err;
wire [31:0] wbu_wbu_arbiter_idata;
// Verilator lint_on UNUSED
// Wishbone definitions for bus wbu, component zip
// Verilator lint_off UNUSED
wire wbu_zip_cyc, wbu_zip_stb, wbu_zip_we;
wire [26:0] wbu_zip_addr;
wire [31:0] wbu_zip_data;
wire [3:0] wbu_zip_sel;
wire wbu_zip_stall, wbu_zip_ack, wbu_zip_err;
wire [31:0] wbu_zip_idata;
// Verilator lint_on UNUSED
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Peripheral address decoding, bus handling
// {{{
//
// BUS-LOGIC for wbwide
// {{{
//
// No class SINGLE peripherals on the "wbwide" bus
//
//
// No class DOUBLE peripherals on the "wbwide" bus
//
// info: @ERROR.WIRE for wbdown matches the buses error name, wbwide_wbdown_err
assign wbwide_bkram_err= 1'b0;
assign wbwide_ddr3_controller_err= 1'b0;
//
// Connect the wbwide bus components together using the wbxbar()
//
//
wbxbar #(
.NM(4), .NS(3), .AW(22), .DW(512),
.SLAVE_ADDR({
// Address width = 22
// Address LSBs = 6
// Slave name width = 15
{ 22'h200000 }, // ddr3_controller: 0x8000000
{ 22'h100000 }, // bkram: 0x4000000
{ 22'h080000 } // wbdown: 0x2000000
}),
.SLAVE_MASK({
// Address width = 22
// Address LSBs = 6
// Slave name width = 15
{ 22'h200000 }, // ddr3_controller
{ 22'h380000 }, // bkram
{ 22'h380000 } // wbdown
}),
.OPT_DBLBUFFER(1'b1))
wbwide_xbar(
.i_clk(i_clk), .i_reset(i_reset),
.i_mcyc({
wbwide_wbu_arbiter_cyc,
wbwide_zip_cyc,
wbwide_i2cm_cyc,
wbwide_i2cdma_cyc
}),
.i_mstb({
wbwide_wbu_arbiter_stb,
wbwide_zip_stb,
wbwide_i2cm_stb,
wbwide_i2cdma_stb
}),
.i_mwe({
wbwide_wbu_arbiter_we,
wbwide_zip_we,
wbwide_i2cm_we,
wbwide_i2cdma_we
}),
.i_maddr({
wbwide_wbu_arbiter_addr,
wbwide_zip_addr,
wbwide_i2cm_addr,
wbwide_i2cdma_addr
}),
.i_mdata({
wbwide_wbu_arbiter_data,
wbwide_zip_data,
wbwide_i2cm_data,
wbwide_i2cdma_data
}),
.i_msel({
wbwide_wbu_arbiter_sel,
wbwide_zip_sel,
wbwide_i2cm_sel,
wbwide_i2cdma_sel
}),
.o_mstall({
wbwide_wbu_arbiter_stall,
wbwide_zip_stall,
wbwide_i2cm_stall,
wbwide_i2cdma_stall
}),
.o_mack({
wbwide_wbu_arbiter_ack,
wbwide_zip_ack,
wbwide_i2cm_ack,
wbwide_i2cdma_ack
}),
.o_mdata({
wbwide_wbu_arbiter_idata,
wbwide_zip_idata,
wbwide_i2cm_idata,
wbwide_i2cdma_idata
}),
.o_merr({
wbwide_wbu_arbiter_err,
wbwide_zip_err,
wbwide_i2cm_err,
wbwide_i2cdma_err
}),
// Slave connections
.o_scyc({
wbwide_ddr3_controller_cyc,
wbwide_bkram_cyc,
wbwide_wbdown_cyc
}),
.o_sstb({
wbwide_ddr3_controller_stb,
wbwide_bkram_stb,
wbwide_wbdown_stb
}),
.o_swe({
wbwide_ddr3_controller_we,
wbwide_bkram_we,
wbwide_wbdown_we
}),
.o_saddr({
wbwide_ddr3_controller_addr,
wbwide_bkram_addr,
wbwide_wbdown_addr
}),
.o_sdata({
wbwide_ddr3_controller_data,
wbwide_bkram_data,
wbwide_wbdown_data
}),
.o_ssel({
wbwide_ddr3_controller_sel,
wbwide_bkram_sel,
wbwide_wbdown_sel
}),
.i_sstall({
wbwide_ddr3_controller_stall,
wbwide_bkram_stall,
wbwide_wbdown_stall
}),
.i_sack({
wbwide_ddr3_controller_ack,
wbwide_bkram_ack,
wbwide_wbdown_ack
}),
.i_sdata({
wbwide_ddr3_controller_idata,
wbwide_bkram_idata,
wbwide_wbdown_idata
}),
.i_serr({
wbwide_ddr3_controller_err,
wbwide_bkram_err,
wbwide_wbdown_err
})
);
// End of bus logic for wbwide
// }}}
//
// BUS-LOGIC for wb32
// {{{
//
// wb32 Bus logic to handle SINGLE slaves
//
reg r_wb32_sio_ack;
reg [31:0] r_wb32_sio_data;
assign wb32_sio_stall = 1'b0;
initial r_wb32_sio_ack = 1'b0;
always @(posedge i_clk)
r_wb32_sio_ack <= (wb32_sio_stb);
assign wb32_sio_ack = r_wb32_sio_ack;
always @(posedge i_clk)
casez( wb32_sio_addr[2:0] )
3'h0: r_wb32_sio_data <= wb32_buildtime_idata;
3'h1: r_wb32_sio_data <= wb32_gpio_idata;
3'h2: r_wb32_sio_data <= wb32_sirefclk_idata;
3'h3: r_wb32_sio_data <= wb32_spio_idata;
3'h4: r_wb32_sio_data <= wb32_version_idata;
default: r_wb32_sio_data <= wb32_version_idata;
endcase
assign wb32_sio_idata = r_wb32_sio_data;
//
// Now to translate this logic to the various SIO slaves
//
// In this case, the SIO bus has the prefix wb32_sio
// and all of the slaves have various wires beginning
// with their own respective bus prefixes.
// Our goal here is to make certain that all of
// the slave bus inputs match the SIO bus wires
assign wb32_buildtime_cyc = wb32_sio_cyc;
assign wb32_buildtime_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h0); // 0x00
assign wb32_buildtime_we = wb32_sio_we;
assign wb32_buildtime_data= wb32_sio_data;
assign wb32_buildtime_sel = wb32_sio_sel;
assign wb32_gpio_cyc = wb32_sio_cyc;
assign wb32_gpio_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h1); // 0x04
assign wb32_gpio_we = wb32_sio_we;
assign wb32_gpio_data= wb32_sio_data;
assign wb32_gpio_sel = wb32_sio_sel;
assign wb32_sirefclk_cyc = wb32_sio_cyc;
assign wb32_sirefclk_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h2); // 0x08
assign wb32_sirefclk_we = wb32_sio_we;
assign wb32_sirefclk_data= wb32_sio_data;
assign wb32_sirefclk_sel = wb32_sio_sel;
assign wb32_spio_cyc = wb32_sio_cyc;
assign wb32_spio_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h3); // 0x0c
assign wb32_spio_we = wb32_sio_we;
assign wb32_spio_data= wb32_sio_data;
assign wb32_spio_sel = wb32_sio_sel;
assign wb32_version_cyc = wb32_sio_cyc;
assign wb32_version_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h4); // 0x10
assign wb32_version_we = wb32_sio_we;
assign wb32_version_data= wb32_sio_data;
assign wb32_version_sel = wb32_sio_sel;
//
// No class DOUBLE peripherals on the "wb32" bus
//
assign wb32_emmcscope_err= 1'b0;
assign wb32_i2cscope_err= 1'b0;
assign wb32_sdioscope_err= 1'b0;
assign wb32_i2cs_err= 1'b0;
assign wb32_i2cdma_err= 1'b0;
assign wb32_uart_err= 1'b0;
assign wb32_emmc_err= 1'b0;
assign wb32_fan_err= 1'b0;
assign wb32_sdcard_err= 1'b0;
assign wb32_sio_err= 1'b0;
assign wb32_cfg_err= 1'b0;
assign wb32_ddr3_phy_err= 1'b0;
//
// Connect the wb32 bus components together using the wbxbar()
//
//
wbxbar #(
.NM(1), .NS(12), .AW(8), .DW(32),
.SLAVE_ADDR({
// Address width = 8
// Address LSBs = 2
// Slave name width = 9
{ 8'h80 }, // ddr3_phy: 0x200
{ 8'h60 }, // cfg: 0x180
{ 8'h48 }, // wb32_sio: 0x120
{ 8'h40 }, // sdcard: 0x100
{ 8'h38 }, // fan: 0x0e0
{ 8'h30 }, // emmc: 0x0c0
{ 8'h28 }, // uart: 0x0a0
{ 8'h20 }, // i2cdma: 0x080
{ 8'h18 }, // i2c: 0x060
{ 8'h10 }, // sdioscope: 0x040
{ 8'h08 }, // i2cscope: 0x020
{ 8'h00 } // emmcscope: 0x000
}),
.SLAVE_MASK({
// Address width = 8
// Address LSBs = 2
// Slave name width = 9
{ 8'h80 }, // ddr3_phy
{ 8'he0 }, // cfg
{ 8'hf8 }, // wb32_sio
{ 8'hf8 }, // sdcard
{ 8'hf8 }, // fan
{ 8'hf8 }, // emmc
{ 8'hf8 }, // uart
{ 8'hf8 }, // i2cdma
{ 8'hf8 }, // i2c
{ 8'hf8 }, // sdioscope
{ 8'hf8 }, // i2cscope
{ 8'hf8 } // emmcscope
}),
.OPT_DBLBUFFER(1'b1))
wb32_xbar(
.i_clk(i_clk), .i_reset(i_reset),
.i_mcyc({
wb32_wbdown_cyc
}),
.i_mstb({
wb32_wbdown_stb
}),
.i_mwe({
wb32_wbdown_we
}),
.i_maddr({
wb32_wbdown_addr
}),
.i_mdata({
wb32_wbdown_data
}),
.i_msel({
wb32_wbdown_sel
}),
.o_mstall({
wb32_wbdown_stall
}),
.o_mack({
wb32_wbdown_ack
}),
.o_mdata({
wb32_wbdown_idata
}),
.o_merr({
wb32_wbdown_err
}),
// Slave connections
.o_scyc({
wb32_ddr3_phy_cyc,
wb32_cfg_cyc,
wb32_sio_cyc,
wb32_sdcard_cyc,
wb32_fan_cyc,
wb32_emmc_cyc,
wb32_uart_cyc,
wb32_i2cdma_cyc,
wb32_i2cs_cyc,
wb32_sdioscope_cyc,
wb32_i2cscope_cyc,
wb32_emmcscope_cyc
}),
.o_sstb({
wb32_ddr3_phy_stb,
wb32_cfg_stb,
wb32_sio_stb,
wb32_sdcard_stb,
wb32_fan_stb,
wb32_emmc_stb,
wb32_uart_stb,
wb32_i2cdma_stb,
wb32_i2cs_stb,
wb32_sdioscope_stb,
wb32_i2cscope_stb,
wb32_emmcscope_stb
}),
.o_swe({
wb32_ddr3_phy_we,
wb32_cfg_we,
wb32_sio_we,
wb32_sdcard_we,
wb32_fan_we,
wb32_emmc_we,
wb32_uart_we,
wb32_i2cdma_we,
wb32_i2cs_we,
wb32_sdioscope_we,
wb32_i2cscope_we,
wb32_emmcscope_we
}),
.o_saddr({
wb32_ddr3_phy_addr,
wb32_cfg_addr,
wb32_sio_addr,
wb32_sdcard_addr,
wb32_fan_addr,
wb32_emmc_addr,
wb32_uart_addr,
wb32_i2cdma_addr,
wb32_i2cs_addr,
wb32_sdioscope_addr,
wb32_i2cscope_addr,
wb32_emmcscope_addr
}),
.o_sdata({
wb32_ddr3_phy_data,
wb32_cfg_data,
wb32_sio_data,
wb32_sdcard_data,
wb32_fan_data,
wb32_emmc_data,
wb32_uart_data,
wb32_i2cdma_data,
wb32_i2cs_data,
wb32_sdioscope_data,
wb32_i2cscope_data,
wb32_emmcscope_data
}),
.o_ssel({
wb32_ddr3_phy_sel,
wb32_cfg_sel,
wb32_sio_sel,
wb32_sdcard_sel,
wb32_fan_sel,
wb32_emmc_sel,
wb32_uart_sel,
wb32_i2cdma_sel,
wb32_i2cs_sel,
wb32_sdioscope_sel,
wb32_i2cscope_sel,
wb32_emmcscope_sel
}),
.i_sstall({
wb32_ddr3_phy_stall,
wb32_cfg_stall,
wb32_sio_stall,
wb32_sdcard_stall,
wb32_fan_stall,
wb32_emmc_stall,
wb32_uart_stall,
wb32_i2cdma_stall,
wb32_i2cs_stall,
wb32_sdioscope_stall,
wb32_i2cscope_stall,
wb32_emmcscope_stall
}),
.i_sack({
wb32_ddr3_phy_ack,
wb32_cfg_ack,
wb32_sio_ack,
wb32_sdcard_ack,
wb32_fan_ack,
wb32_emmc_ack,
wb32_uart_ack,
wb32_i2cdma_ack,
wb32_i2cs_ack,
wb32_sdioscope_ack,
wb32_i2cscope_ack,
wb32_emmcscope_ack
}),
.i_sdata({
wb32_ddr3_phy_idata,
wb32_cfg_idata,
wb32_sio_idata,
wb32_sdcard_idata,
wb32_fan_idata,
wb32_emmc_idata,
wb32_uart_idata,
wb32_i2cdma_idata,
wb32_i2cs_idata,
wb32_sdioscope_idata,
wb32_i2cscope_idata,
wb32_emmcscope_idata
}),
.i_serr({
wb32_ddr3_phy_err,
wb32_cfg_err,
wb32_sio_err,
wb32_sdcard_err,
wb32_fan_err,
wb32_emmc_err,
wb32_uart_err,
wb32_i2cdma_err,
wb32_i2cs_err,
wb32_sdioscope_err,
wb32_i2cscope_err,
wb32_emmcscope_err
})
);
// End of bus logic for wb32
// }}}
//
// BUS-LOGIC for wbu
// {{{
//
// No class SINGLE peripherals on the "wbu" bus
//
//
// No class DOUBLE peripherals on the "wbu" bus
//
// info: @ERROR.WIRE for wbu_arbiter matches the buses error name, wbu_wbu_arbiter_err
assign wbu_zip_err= 1'b0;
//
// Connect the wbu bus components together using the wbxbar()
//
//
wbxbar #(
.NM(1), .NS(2), .AW(27), .DW(32),
.SLAVE_ADDR({
// Address width = 27
// Address LSBs = 2
// Slave name width = 11
{ 27'h4000000 }, // zip: 0x10000000
{ 27'h0000000 } // wbu_arbiter: 0x00000000
}),
.SLAVE_MASK({
// Address width = 27
// Address LSBs = 2
// Slave name width = 11
{ 27'h4000000 }, // zip
{ 27'h4000000 } // wbu_arbiter
}),
.OPT_DBLBUFFER(1'b1))
wbu_xbar(
.i_clk(i_clk), .i_reset(i_reset),
.i_mcyc({
wbu_cyc
}),
.i_mstb({
wbu_stb
}),
.i_mwe({
wbu_we
}),
.i_maddr({
wbu_addr
}),
.i_mdata({
wbu_data
}),
.i_msel({
wbu_sel
}),
.o_mstall({
wbu_stall
}),
.o_mack({
wbu_ack
}),
.o_mdata({
wbu_idata
}),
.o_merr({
wbu_err
}),
// Slave connections
.o_scyc({
wbu_zip_cyc,
wbu_wbu_arbiter_cyc
}),
.o_sstb({
wbu_zip_stb,
wbu_wbu_arbiter_stb
}),
.o_swe({
wbu_zip_we,
wbu_wbu_arbiter_we
}),
.o_saddr({
wbu_zip_addr,
wbu_wbu_arbiter_addr
}),
.o_sdata({
wbu_zip_data,
wbu_wbu_arbiter_data
}),
.o_ssel({
wbu_zip_sel,
wbu_wbu_arbiter_sel
}),
.i_sstall({
wbu_zip_stall,
wbu_wbu_arbiter_stall
}),
.i_sack({
wbu_zip_ack,
wbu_wbu_arbiter_ack
}),
.i_sdata({
wbu_zip_idata,
wbu_wbu_arbiter_idata
}),
.i_serr({
wbu_zip_err,
wbu_wbu_arbiter_err
})
);
// End of bus logic for wbu
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Declare the interrupt busses
// {{{
// Interrupt busses are defined by anything with a @PIC tag.
// The @PIC.BUS tag defines the name of the wire bus below,
// while the @PIC.MAX tag determines the size of the bus width.
//
// For your peripheral to be assigned to this bus, it must have an
// @INT.NAME.WIRE= tag to define the wire name of the interrupt line,
// and an @INT.NAME.PIC= tag matching the @PIC.BUS tag of the bus
// your interrupt will be assigned to. If an @INT.NAME.ID tag also
// exists, then your interrupt will be assigned to the position given
// by the ID# in that tag.
//
assign sys_int_vector = {
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
spio_int,
uarttxf_int,
uartrxf_int,
sdcard_int,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0
};
assign alt_int_vector = {
gpio_int,
i2cscope_int,
uartrx_int,
uarttx_int,
emmc_int,
sdioscope_int,
emmcscope_int,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0
};
// }}}
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
// @MAIN.INSERT and @MAIN.ALT
// {{{
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
//
// Now we turn to defining all of the parts and pieces of what
// each of the various peripherals does, and what logic it needs.
//
// This information comes from the @MAIN.INSERT and @MAIN.ALT tags.
// If an @ACCESS tag is available, an ifdef is created to handle
// having the access and not. If the @ACCESS tag is `defined above
// then the @MAIN.INSERT code is executed. If not, the @MAIN.ALT
// code is exeucted, together with any other cleanup settings that
// might need to take place--such as returning zeros to the bus,
// or making sure all of the various interrupt wires are set to
// zero if the component is not included.
//
`ifdef EMMCSCOPE_SCOPC
// {{{
wbscopc #(
// {{{
.LGMEM(12),
.SYNCHRONOUS(1),
.DEFAULT_HOLDOFF(2044)
// }}}
) emmcscopei(
// {{{
i_clk, 1'b1, emmc_debug[31], emmc_debug[30:0],
i_clk,
wb32_emmcscope_cyc, wb32_emmcscope_stb, wb32_emmcscope_we,
wb32_emmcscope_addr[1-1:0],
wb32_emmcscope_data, // 32 bits wide
wb32_emmcscope_sel, // 32/8 bits wide
wb32_emmcscope_stall, wb32_emmcscope_ack, wb32_emmcscope_idata,
emmcscope_int
// }}}
);
// }}}
`else // EMMCSCOPE_SCOPC
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb32_emmcscope peripheral
// responding on the wb32 bus
assign wb32_emmcscope_ack = 1'b0;
assign wb32_emmcscope_err = (wb32_emmcscope_stb);
assign wb32_emmcscope_stall = 0;
assign wb32_emmcscope_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign emmcscope_int = 1'b0; // emmcscope.INT.EMMCSCOPE.WIRE
// }}}
// }}}
`endif // EMMCSCOPE_SCOPC
`ifdef SDIOSCOPE_SCOPC
// {{{
wbscopc #(
// {{{
.LGMEM(12),
.SYNCHRONOUS(1),
.DEFAULT_HOLDOFF(2044)
// }}}
) sdioscopei(
// {{{
i_clk, 1'b1, sdcard_debug[31], sdcard_debug[30:0],
i_clk,
wb32_sdioscope_cyc, wb32_sdioscope_stb, wb32_sdioscope_we,
wb32_sdioscope_addr[1-1:0],
wb32_sdioscope_data, // 32 bits wide
wb32_sdioscope_sel, // 32/8 bits wide
wb32_sdioscope_stall, wb32_sdioscope_ack, wb32_sdioscope_idata,
sdioscope_int
// }}}
);
// }}}
`else // SDIOSCOPE_SCOPC
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb32_sdioscope peripheral
// responding on the wb32 bus
assign wb32_sdioscope_ack = 1'b0;
assign wb32_sdioscope_err = (wb32_sdioscope_stb);
assign wb32_sdioscope_stall = 0;
assign wb32_sdioscope_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign sdioscope_int = 1'b0; // sdioscope.INT.SDIOSCOPE.WIRE
// }}}
// }}}
`endif // SDIOSCOPE_SCOPC
`ifdef DDR3_CONTROLLER_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// DDR3 Controller instantiation
// {{{
ddr3_controller #(
.CONTROLLER_CLK_PERIOD(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module
.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device
.ROW_BITS(DDR3_CONTROLLERROW_BITS), //width of row address
.COL_BITS(DDR3_CONTROLLERCOL_BITS), //width of column address
.BA_BITS(DDR3_CONTROLLERBA_BITS), //width of bank address
.DQ_BITS(DDR3_CONTROLLERDQ_BITS), //width of DQ
.LANES(DDR3_CONTROLLERLANES), //8 lanes of DQ
.AUX_WIDTH(DDR3_CONTROLLERAUX_WIDTH), //
.OPT_LOWPOWER(1), //1 = low power, 0 = low logic
.OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
) ddr3_controller_inst (
.i_controller_clk(i_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD
.i_rst_n(!i_reset), //200MHz input clock
// Wishbone 1 (Controller)
.i_wb_cyc(wbwide_ddr3_controller_cyc), .i_wb_stb(wbwide_ddr3_controller_stb), .i_wb_we(wbwide_ddr3_controller_we),
.i_wb_addr(wbwide_ddr3_controller_addr[21-1:0]),
.i_wb_data(wbwide_ddr3_controller_data), // 512 bits wide
.i_wb_sel(wbwide_ddr3_controller_sel), // 512/8 bits wide
.o_wb_stall(wbwide_ddr3_controller_stall),.o_wb_ack(wbwide_ddr3_controller_ack), .o_wb_data(wbwide_ddr3_controller_idata),
.i_aux(0),
.o_aux(ddr3_controller_aux_out), // Leaving this empty would've caused a Verilator warning
// Wishbone 2 (PHY)
.i_wb2_cyc(wb32_ddr3_phy_cyc), .i_wb2_stb(wb32_ddr3_phy_stb), .i_wb2_we(wb32_ddr3_phy_we),
.i_wb2_addr(wb32_ddr3_phy_addr[7-1:0]),
.i_wb2_data(wb32_ddr3_phy_data), // 32 bits wide
.i_wb2_sel(wb32_ddr3_phy_sel), // 32/8 bits wide
.o_wb2_stall(wb32_ddr3_phy_stall),.o_wb2_ack(wb32_ddr3_phy_ack), .o_wb2_data(wb32_ddr3_phy_idata),
//
// PHY interface
.i_phy_iserdes_data(i_ddr3_controller_iserdes_data),
.i_phy_iserdes_dqs(i_ddr3_controller_iserdes_dqs),
.i_phy_iserdes_bitslip_reference(i_ddr3_controller_iserdes_bitslip_reference),
.i_phy_idelayctrl_rdy(i_ddr3_controller_idelayctrl_rdy),
.o_phy_cmd(o_ddr3_controller_cmd),
.o_phy_dqs_tri_control(o_ddr3_controller_dqs_tri_control),
.o_phy_dq_tri_control(o_ddr3_controller_dq_tri_control),
.o_phy_toggle_dqs(o_ddr3_controller_toggle_dqs),
.o_phy_data(o_ddr3_controller_data),
.o_phy_dm(o_ddr3_controller_dm),
.o_phy_odelay_data_cntvaluein(o_ddr3_controller_odelay_data_cntvaluein),
.o_phy_odelay_dqs_cntvaluein(o_ddr3_controller_odelay_dqs_cntvaluein),
.o_phy_idelay_data_cntvaluein(o_ddr3_controller_idelay_data_cntvaluein),
.o_phy_idelay_dqs_cntvaluein(o_ddr3_controller_idelay_dqs_cntvaluein),
.o_phy_odelay_data_ld(o_ddr3_controller_odelay_data_ld),
.o_phy_odelay_dqs_ld(o_ddr3_controller_odelay_dqs_ld),
.o_phy_idelay_data_ld(o_ddr3_controller_idelay_data_ld),
.o_phy_idelay_dqs_ld(o_ddr3_controller_idelay_dqs_ld),
.o_phy_bitslip(o_ddr3_controller_bitslip)
);
// }}}
// }}}
`else // DDR3_CONTROLLER_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wbwide_ddr3_controller peripheral
// responding on the wbwide bus
assign wbwide_ddr3_controller_ack = 1'b0;
assign wbwide_ddr3_controller_err = (wbwide_ddr3_controller_stb);
assign wbwide_ddr3_controller_stall = 0;
assign wbwide_ddr3_controller_idata = 0;
// }}}
// }}}
`endif // DDR3_CONTROLLER_ACCESS
`ifdef BKRAM_ACCESS
// {{{
memdev #(
.LGMEMSZ(20),
.DW(512),
.EXTRACLOCK(1)
) bkrami(
.i_clk(i_clk),
.i_reset(i_reset),
.i_wb_cyc(wbwide_bkram_cyc), .i_wb_stb(wbwide_bkram_stb), .i_wb_we(wbwide_bkram_we),
.i_wb_addr(wbwide_bkram_addr[14-1:0]),
.i_wb_data(wbwide_bkram_data), // 512 bits wide
.i_wb_sel(wbwide_bkram_sel), // 512/8 bits wide
.o_wb_stall(wbwide_bkram_stall),.o_wb_ack(wbwide_bkram_ack), .o_wb_data(wbwide_bkram_idata)
);
// }}}
`else // BKRAM_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wbwide_bkram peripheral
// responding on the wbwide bus
assign wbwide_bkram_ack = 1'b0;
assign wbwide_bkram_err = (wbwide_bkram_stb);
assign wbwide_bkram_stall = 0;
assign wbwide_bkram_idata = 0;
// }}}
// }}}
`endif // BKRAM_ACCESS
`ifdef SIREFCLK_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// Generated clock handling
// {{{
//
// Set to 0x2f85_1ec0 for 148.5MHz
//
initial r_sirefclk_en = 1'b0;
initial r_sirefclk_data = 30'd20000;
always @(posedge i_clk)
if (wb32_sirefclk_stb && wb32_sirefclk_we)
begin
if (wb32_sirefclk_sel[0])
r_sirefclk_data[ 7: 0] <= wb32_sirefclk_data[ 7:0];
if (wb32_sirefclk_sel[1])
r_sirefclk_data[15: 8] <= wb32_sirefclk_data[15:8];
if (wb32_sirefclk_sel[2])
r_sirefclk_data[23:16] <= wb32_sirefclk_data[23:16];
if (wb32_sirefclk_sel[3])
begin
r_sirefclk_en <= !wb32_sirefclk_data[31];
r_sirefclk_data[29:24]<= wb32_sirefclk_data[29:24];
end
end
always @(posedge i_clk)
if (i_reset)
r_sirefclk_ack <= 1'b0;
else
r_sirefclk_ack <= wb32_sirefclk_stb;
assign wb32_sirefclk_ack = r_sirefclk_ack;
assign wb32_sirefclk_stall = 1'b0;
assign wb32_sirefclk_idata = { !r_sirefclk_en,
1'b0, r_sirefclk_data };
assign o_sirefclk_ce = r_sirefclk_en;
genclk
clock_generator(
.i_clk(i_clk),
.i_delay({ 2'b00, r_sirefclk_data[29:0] }),
.o_word(o_sirefclk_word),
.o_stb(w_sirefclk_unused_stb)
);
// }}}
// }}}
`else // SIREFCLK_ACCESS
// {{{
// }}}
`endif // SIREFCLK_ACCESS
`ifdef I2CDMA_ACCESS
// {{{
wbi2cdma #(
.AW(22), .DW(512), .SW(8),
.OPT_LITTLE_ENDIAN(1'b0)
) u_i2cdma (
.i_clk(i_clk),
.i_reset(i_reset),
//
.i_wb_cyc(wb32_i2cdma_cyc), .i_wb_stb(wb32_i2cdma_stb), .i_wb_we(wb32_i2cdma_we),
.i_wb_addr(wb32_i2cdma_addr[2-1:0]),
.i_wb_data(wb32_i2cdma_data), // 32 bits wide
.i_wb_sel(wb32_i2cdma_sel), // 32/8 bits wide
.o_wb_stall(wb32_i2cdma_stall),.o_wb_ack(wb32_i2cdma_ack), .o_wb_data(wb32_i2cdma_idata),
.S_VALID(i2c_valid && i2c_id == 2), .S_READY(i2cdma_ready),
.S_DATA(i2c_data), .S_LAST(i2c_last),
.o_dma_cyc(wbwide_i2cdma_cyc), .o_dma_stb(wbwide_i2cdma_stb), .o_dma_we(wbwide_i2cdma_we),
.o_dma_addr(wbwide_i2cdma_addr[22-1:0]),
.o_dma_data(wbwide_i2cdma_data), // 512 bits wide
.o_dma_sel(wbwide_i2cdma_sel), // 512/8 bits wide
.i_dma_stall(wbwide_i2cdma_stall), .i_dma_ack(wbwide_i2cdma_ack), .i_dma_data(wbwide_i2cdma_idata), .i_dma_err(wbwide_i2cdma_err)
);
// }}}
`else // I2CDMA_ACCESS
// {{{
assign @$(prefix)_ready = 1'b0;
// Null bus master
// {{{
// }}}
// Null bus slave
// {{{
//
// In the case that there is no wb32_i2cdma peripheral
// responding on the wb32 bus
assign wb32_i2cdma_ack = 1'b0;
assign wb32_i2cdma_err = (wb32_i2cdma_stb);
assign wb32_i2cdma_stall = 0;
assign wb32_i2cdma_idata = 0;
// }}}
// }}}
`endif // I2CDMA_ACCESS
`ifdef FAN_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// The FAN Controller: fan
// {{{
wbfan
u_fan (
// {{{
.i_clk(i_clk),
.i_reset(i_reset),
.i_wb_cyc(wb32_fan_cyc), .i_wb_stb(wb32_fan_stb), .i_wb_we(wb32_fan_we),
.i_wb_addr(wb32_fan_addr[3-1:0]),
.i_wb_data(wb32_fan_data), // 32 bits wide
.i_wb_sel(wb32_fan_sel), // 32/8 bits wide
.o_wb_stall(wb32_fan_stall),.o_wb_ack(wb32_fan_ack), .o_wb_data(wb32_fan_idata),
.i_temp_sda(i_fan_sda), .i_temp_scl(i_fan_scl),
.o_temp_sda(o_fan_sda), .o_temp_scl(o_fan_scl),
//
.o_fpga_pwm(o_fpga_pwm), .o_sys_pwm(o_sys_pwm),
.i_fan_tach(i_fan_tach),
//
.temp_debug(fan_debug)
// }}}
);
// }}}
// }}}
`else // FAN_ACCESS
// {{{
assign o_fan_scl = 1'b1;
assign o_fan_sda = 1'b1;
// Null bus slave
// {{{
//
// In the case that there is no wb32_fan peripheral
// responding on the wb32 bus
assign wb32_fan_ack = 1'b0;
assign wb32_fan_err = (wb32_fan_stb);
assign wb32_fan_stall = 0;
assign wb32_fan_idata = 0;
// }}}
// }}}
`endif // FAN_ACCESS
`ifdef EMMC_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// eMMC Card handling
// {{{
////////////////////////////////////////////////////////////////////////
//
//
sdio_top #(
.NUMIO(8),
.OPT_SERDES(1'b0),
.OPT_DDR(1'b0),
.OPT_CARD_DETECT(1'b0),
.MW(32)
) u_emmc(
// {{{
.i_clk(i_clk),
.i_reset(i_reset),
.i_hsclk(1'b0),
.i_wb_cyc(wb32_emmc_cyc), .i_wb_stb(wb32_emmc_stb), .i_wb_we(wb32_emmc_we),
.i_wb_addr(wb32_emmc_addr[3-1:0]),
.i_wb_data(wb32_emmc_data), // 32 bits wide
.i_wb_sel(wb32_emmc_sel), // 32/8 bits wide
.o_wb_stall(wb32_emmc_stall),.o_wb_ack(wb32_emmc_ack), .o_wb_data(wb32_emmc_idata),
.o_ck(o_emmc_clk),
.i_ds(i_emmc_ds),
`ifdef VERILATOR
.io_cmd_tristate(io_emmc_cmd_tristate),
.o_cmd(o_emmc_cmd),
.i_cmd(i_emmc_cmd),
.io_dat_tristate(io_emmc_dat_tristate),
.o_dat(o_emmc_dat),
.i_dat(i_emmc_dat),
`else
.io_cmd(io_emmc_cmd),
.io_dat(io_emmc_dat),
`endif
.i_card_detect(i_emmc_detect),
.o_1p8v(w_emmc_1p8v),
.o_int(emmc_int),
.o_debug(emmc_debug)
// }}}
);
// }}}
// }}}
`else // EMMC_ACCESS
// {{{
assign o_emmc_clk = 1'b1;
`ifdef VERILATOR
assign io_emmc_cmd_tristate = 1'b1;
assign o_emmc_cmd = 1'b1;
assign io_emmc_data_tristate = -1;
assign o_emmc_data = -1;
`else // VERILATOR
assign io_emmc_cmd = 1'b1;
assign io_emmc_dat = -1;
`endif // VERILATOR
// Null bus slave
// {{{
//
// In the case that there is no wb32_emmc peripheral
// responding on the wb32 bus
assign wb32_emmc_ack = 1'b0;
assign wb32_emmc_err = (wb32_emmc_stb);
assign wb32_emmc_stall = 0;
assign wb32_emmc_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign emmc_int = 1'b0; // emmc.INT.EMMC.WIRE
// }}}
// }}}
`endif // EMMC_ACCESS
`ifdef I2CCPU_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// The I2C Controller
// {{{
wbi2ccpu #(
.ADDRESS_WIDTH(22),
.DATA_WIDTH(512),
.AXIS_ID_WIDTH(2)
) i2ci (
// {{{
.i_clk(i_clk), .i_reset(i_reset),
.i_wb_cyc(wb32_i2cs_cyc), .i_wb_stb(wb32_i2cs_stb), .i_wb_we(wb32_i2cs_we),
.i_wb_addr(wb32_i2cs_addr[2-1:0]),
.i_wb_data(wb32_i2cs_data), // 32 bits wide
.i_wb_sel(wb32_i2cs_sel), // 32/8 bits wide
.o_wb_stall(wb32_i2cs_stall),.o_wb_ack(wb32_i2cs_ack), .o_wb_data(wb32_i2cs_idata),
.o_pf_cyc(wbwide_i2cm_cyc), .o_pf_stb(wbwide_i2cm_stb), .o_pf_we(wbwide_i2cm_we),
.o_pf_addr(wbwide_i2cm_addr[22-1:0]),
.o_pf_data(wbwide_i2cm_data), // 512 bits wide
.o_pf_sel(wbwide_i2cm_sel), // 512/8 bits wide
.i_pf_stall(wbwide_i2cm_stall), .i_pf_ack(wbwide_i2cm_ack), .i_pf_data(wbwide_i2cm_idata), .i_pf_err(wbwide_i2cm_err),
.i_i2c_sda(i_i2c_sda), .i_i2c_scl(i_i2c_scl),
.o_i2c_sda(o_i2c_sda), .o_i2c_scl(o_i2c_scl),
.M_AXIS_TVALID(i2c_valid), .M_AXIS_TREADY(i2c_ready),
.M_AXIS_TDATA(i2c_data), .M_AXIS_TLAST(i2c_last),
.M_AXIS_TID(i2c_id),
.i_sync_signal(1'b0),
//
.o_debug(i2c_debug)
// }}}
);
assign i2c_ready = (!i2c_valid) || (1'b0
|| (i2c_id == 0) // NULL address
`ifdef EDID_ACCESS
|| (i2c_id == 1 && edid_ready)
`else
|| (i2c_id == 1)
`endif
`ifdef I2CDMA_ACCESS
|| (i2c_id == 2 && i2cdma_ready)
`else
|| (i2c_id == 2)
`endif
|| (i2c_id > 2));
// }}}
// }}}
`else // I2CCPU_ACCESS
// {{{
assign o_i2c_scl = 1'b1;
assign o_i2c_sda = 1'b1;
// Null bus master
// {{{
// }}}
// Null bus slave
// {{{
//
// In the case that there is no wb32_i2cs peripheral
// responding on the wb32 bus
assign wb32_i2cs_ack = 1'b0;
assign wb32_i2cs_err = (wb32_i2cs_stb);
assign wb32_i2cs_stall = 0;
assign wb32_i2cs_idata = 0;
// }}}
// }}}
`endif // I2CCPU_ACCESS
wbdown #(
// {{{
.ADDRESS_WIDTH(8+$clog2(32/8)),
.WIDE_DW(512),
.SMALL_DW(32),
.OPT_LITTLE_ENDIAN(1'b0),
.OPT_LOWLOGIC(1'b0)
// }}}
) u_wbdown (
// {{{
.i_clk(i_clk),
.i_reset(i_reset),
// Slave/incoming
// {{{
.i_wcyc( wbwide_wbdown_cyc),
.i_wstb( wbwide_wbdown_stb),
.i_wwe( wbwide_wbdown_we),
.i_waddr( wbwide_wbdown_addr[4-1:0]),
.i_wdata( wbwide_wbdown_data),
.i_wsel( wbwide_wbdown_sel),
.o_wstall(wbwide_wbdown_stall),
.o_wack( wbwide_wbdown_ack),
.o_wdata( wbwide_wbdown_idata),
.o_werr( wbwide_wbdown_err),
// }}}
// Master/down-range/outgoing
// {{{
.o_scyc( wb32_wbdown_cyc),
.o_sstb( wb32_wbdown_stb),
.o_swe( wb32_wbdown_we),
.o_saddr( wb32_wbdown_addr[8-1:0]),
.o_sdata( wb32_wbdown_data),
.o_ssel( wb32_wbdown_sel),
.i_sstall(wb32_wbdown_stall),
.i_sack( wb32_wbdown_ack),
.i_sdata( wb32_wbdown_idata),
.i_serr( wb32_wbdown_err)
// }}}
// }}}
);
`ifdef SDIO_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// SDIO SD Card handling
// {{{
////////////////////////////////////////////////////////////////////////
//
//
sdio_top #(
.NUMIO(4),
.OPT_SERDES(1'b0),
.OPT_DDR(1'b1),
.OPT_CARD_DETECT(1'b1),
.MW(32)
) u_sdcard(
// {{{
.i_clk(i_clk),
.i_reset(i_reset),
.i_hsclk(1'b0),
.i_wb_cyc(wb32_sdcard_cyc), .i_wb_stb(wb32_sdcard_stb), .i_wb_we(wb32_sdcard_we),
.i_wb_addr(wb32_sdcard_addr[3-1:0]),
.i_wb_data(wb32_sdcard_data), // 32 bits wide
.i_wb_sel(wb32_sdcard_sel), // 32/8 bits wide
.o_wb_stall(wb32_sdcard_stall),.o_wb_ack(wb32_sdcard_ack), .o_wb_data(wb32_sdcard_idata),
.o_ck(o_sdcard_clk),
.i_ds(i_sdcard_ds),
`ifdef VERILATOR
.io_cmd_tristate(io_sdcard_cmd_tristate),
.o_cmd(o_sdcard_cmd),
.i_cmd(i_sdcard_cmd),
.io_dat_tristate(io_sdcard_dat_tristate),
.o_dat(o_sdcard_dat),
.i_dat(i_sdcard_dat),
`else
.io_cmd(io_sdcard_cmd),
.io_dat(io_sdcard_dat),
`endif
.i_card_detect(i_sdcard_detect),
.o_1p8v(w_sdcard_1p8v),
.o_int(sdcard_int),
.o_debug(sdcard_debug)
// }}}
);
// }}}
// }}}
`else // SDIO_ACCESS
// {{{
assign o_sdcard_clk = 1'b1;
`ifdef VERILATOR
assign io_sdcard_cmd_tristate = 1'b1;
assign o_sdcard_cmd = 1'b1;
assign io_sdcard_data_tristate = -1;
assign o_sdcard_data = -1;
`else // VERILATOR
assign io_sdcard_cmd = 1'b1;
assign io_sdcard_dat = -1;
`endif // VERILATOR
// Null bus slave
// {{{
//
// In the case that there is no wb32_sdcard peripheral
// responding on the wb32 bus
assign wb32_sdcard_ack = 1'b0;
assign wb32_sdcard_err = (wb32_sdcard_stb);
assign wb32_sdcard_stall = 0;
assign wb32_sdcard_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign sdcard_int = 1'b0; // sdcard.INT.SDCARD.WIRE
// }}}
// }}}
`endif // SDIO_ACCESS
assign wb32_buildtime_idata = `BUILDTIME;
assign wb32_buildtime_ack = wb32_buildtime_stb;
assign wb32_buildtime_stall = 1'b0;
`ifdef BUSCONSOLE_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// WBUBUS: Console instantiations
// {{{
wbconsole #(.LGFLEN(6)
) console(
// {{{
.i_clk(i_clk), .i_reset(1'b0),
.i_wb_cyc(wb32_uart_cyc), .i_wb_stb(wb32_uart_stb), .i_wb_we(wb32_uart_we),
.i_wb_addr(wb32_uart_addr[2-1:0]),
.i_wb_data(wb32_uart_data), // 32 bits wide
.i_wb_sel(wb32_uart_sel), // 32/8 bits wide
.o_wb_stall(wb32_uart_stall),.o_wb_ack(wb32_uart_ack), .o_wb_data(wb32_uart_idata),
.o_uart_stb(w_console_tx_stb), .o_uart_data(w_console_tx_data),
`ifdef SMI_CONSOLE
.i_uart_busy(w_console_busy || smi_console_valid),
`else
.i_uart_busy(w_console_busy),
`endif
.i_uart_stb(w_console_rx_stb), .i_uart_data(w_console_rx_data),
.o_uart_rx_int(uartrx_int), .o_uart_tx_int(uarttx_int),
.o_uart_rxfifo_int(uartrxf_int),.o_uart_txfifo_int(uarttxf_int),
.o_debug(uart_debug)
// }}}
);
// }}}
// }}}
`else // BUSCONSOLE_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb32_uart peripheral
// responding on the wb32 bus
assign wb32_uart_ack = 1'b0;
assign wb32_uart_err = (wb32_uart_stb);
assign wb32_uart_stall = 0;
assign wb32_uart_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign uartrxf_int = 1'b0; // uart.INT.UARTRXF.WIRE
assign uarttx_int = 1'b0; // uart.INT.UARTTX.WIRE
assign uarttxf_int = 1'b0; // uart.INT.UARTTXF.WIRE
assign uartrx_int = 1'b0; // uart.INT.UARTRX.WIRE
// }}}
// }}}
`endif // BUSCONSOLE_ACCESS
`ifdef INCLUDE_ZIPCPU
// {{{
////////////////////////////////////////////////////////////////////////
//
// The ZipCPU/ZipSystem BUS master
// {{{
//
assign zip_int_vector = { alt_int_vector[14:8], sys_int_vector[14:6] };
zipsystem #(
// {{{
.RESET_ADDRESS(RESET_ADDRESS),
.ADDRESS_WIDTH(ZIP_ADDRESS_WIDTH + $clog2(512/8)),
.BUS_WIDTH(512),
.OPT_LGICACHE(12),
.OPT_LGDCACHE(12),
.START_HALTED(ZIP_START_HALTED),
.RESET_DURATION(20),
.OPT_PIPELINED(1),
`ifdef INCLUDE_DMA_CONTROLLER
.OPT_DMA(1'b1),
`else
.OPT_DMA(1'b0),
`endif
`ifdef INCLUDE_ACCOUNTING_COUNTERS
.OPT_ACCOUNTING(1'b1),
`else
.OPT_ACCOUNTING(1'b0),
`endif
`ifdef VERILATOR
.OPT_PROFILER(1'b1),
`else
.OPT_PROFILER(1'b0),
`endif
`ifdef ZIPSCOPE_SCOPE
.OPT_TRACE_PORT(1'b1),
`else
.OPT_TRACE_PORT(1'b0),
`endif
.OPT_DISTRIBUTED_REGS(1),
.EXTERNAL_INTERRUPTS(ZIP_INTS)
// }}}
) swic(
// {{{
.i_clk(i_clk), .i_reset(i_reset || i_cpu_reset),
// Zipsys wishbone interface
.o_wb_cyc(wbwide_zip_cyc), .o_wb_stb(wbwide_zip_stb), .o_wb_we(wbwide_zip_we),
.o_wb_addr(wbwide_zip_addr[22-1:0]),
.o_wb_data(wbwide_zip_data), // 512 bits wide
.o_wb_sel(wbwide_zip_sel), // 512/8 bits wide
.i_wb_stall(wbwide_zip_stall), .i_wb_ack(wbwide_zip_ack), .i_wb_data(wbwide_zip_idata), .i_wb_err(wbwide_zip_err),
.i_ext_int(zip_int_vector), .o_ext_int(zip_cpu_int),
// Debug wishbone interface
.i_dbg_cyc(wbu_zip_cyc || cpu_sim_cyc),
.i_dbg_stb(cpu_sim_cyc ? cpu_sim_stb : wbu_zip_stb),
.i_dbg_we( cpu_sim_cyc ? cpu_sim_we : wbu_zip_we),
.i_dbg_addr(cpu_sim_cyc? cpu_sim_addr : wbu_zip_addr[6:0]),
.i_dbg_data (cpu_sim_cyc? cpu_sim_data : wbu_zip_data),
.i_dbg_sel (cpu_sim_cyc? 4'hf : wbu_zip_sel),
.o_dbg_stall(raw_cpu_dbg_stall),
.o_dbg_ack (raw_cpu_dbg_ack),
.o_dbg_data (wbu_zip_idata),
//
.o_cpu_debug(zip_debug),
.o_prof_stb(cpu_prof_stb),
.o_prof_addr(cpu_prof_addr),
.o_prof_ticks(cpu_prof_ticks)
// }}}
);
assign zip_trigger = zip_debug[31];
assign wbu_zip_stall = cpu_sim_cyc || raw_cpu_dbg_stall;
assign wbu_zip_ack = !cpu_sim_cyc && raw_cpu_dbg_ack;
assign cpu_sim_stall = !cpu_sim_cyc || raw_cpu_dbg_stall;
assign cpu_sim_ack = cpu_sim_cyc && raw_cpu_dbg_ack;
assign cpu_sim_idata = wbu_zip_idata;
// Keep Verilator happy
// {{{
// Verilator lint_off UNUSED
wire zip_unused;
assign zip_unused = &{ 1'b0,
alt_int_vector[7:0], sys_int_vector[5:0]};
// Verilator lint_on UNUSED
// }}}
// }}}
// }}}
`else // INCLUDE_ZIPCPU
// {{{
// Null bus master
// {{{
// }}}
// Null bus slave
// {{{
//
// In the case that there is no wbu_zip peripheral
// responding on the wbu bus
assign wbu_zip_ack = 1'b0;
assign wbu_zip_err = (wbu_zip_stb);
assign wbu_zip_stall = 0;
assign wbu_zip_idata = 0;
// }}}
// }}}
`endif // INCLUDE_ZIPCPU
`ifdef VERSION_ACCESS
// {{{
assign wb32_version_idata = `DATESTAMP;
assign wb32_version_ack = wb32_version_stb;
assign wb32_version_stall = 1'b0;
// }}}
`else // VERSION_ACCESS
// {{{
// }}}
`endif // VERSION_ACCESS
`ifdef I2CSCOPE_SCOPC
// {{{
wbscopc #(
// {{{
.LGMEM(10),
.SYNCHRONOUS(1),
.DEFAULT_HOLDOFF(508)
// }}}
) i2cscopei(
// {{{
i_clk, 1'b1, i2c_debug[31], i2c_debug[30:0],
i_clk,
wb32_i2cscope_cyc, wb32_i2cscope_stb, wb32_i2cscope_we,
wb32_i2cscope_addr[1-1:0],
wb32_i2cscope_data, // 32 bits wide
wb32_i2cscope_sel, // 32/8 bits wide
wb32_i2cscope_stall, wb32_i2cscope_ack, wb32_i2cscope_idata,
i2cscope_int
// }}}
);
// }}}
`else // I2CSCOPE_SCOPC
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb32_i2cscope peripheral
// responding on the wb32 bus
assign wb32_i2cscope_ack = 1'b0;
assign wb32_i2cscope_err = (wb32_i2cscope_stb);
assign wb32_i2cscope_stall = 0;
assign wb32_i2cscope_idata = 0;
// }}}
// Null interrupt definitions
// {{{
assign i2cscope_int = 1'b0; // i2cscope.INT.I2CSCOPE.WIRE
// }}}
// }}}
`endif // I2CSCOPE_SCOPC
`ifdef WBUBUS_MASTER
// {{{
////////////////////////////////////////////////////////////////////////
//
// WBUBUS: USB-UART driven bus master and console
// {{{
// The Host USB interface, to be used by the WB-UART bus
rxuartlite #(
// {{{
.TIMER_BITS(DBGBUSBITS),
.CLOCKS_PER_BAUD(BUSUART[DBGBUSBITS-1:0])
// }}}
) rcv(
// {{{
.i_clk( i_clk),
.i_uart_rx(i_wbu_uart_rx),
.o_wr( wbu_rx_stb),
.o_data( wbu_rx_data)
// }}}
);
txuartlite #(
// {{{
.TIMING_BITS(DBGBUSBITS[4:0]),
.CLOCKS_PER_BAUD(BUSUART[DBGBUSBITS-1:0])
// }}}
) txv(
// {{{
.i_clk( i_clk),
.i_wr( wbu_tx_stb),
.i_data( wbu_tx_data),
.o_uart_tx(o_wbu_uart_tx),
.o_busy( wbu_tx_busy)
// }}}
);
assign o_wbu_uart_cts_n = 1'b0;
`ifndef BUSPIC_ACCESS
wire w_bus_int;
`ifdef INCLUDE_ZIPCPU
assign w_bus_int = zip_cpu_int;
`else
assign w_bus_int = 1'b0;
`endif
`endif
// Verilator lint_off UNUSED
wire [29:0] wbu_tmp_addr;
// Verilator lint_on UNUSED
wbuconsole #(
// {{{
.LGWATCHDOG(DBGBUSWATCHDOG)
// }}}
) genbus(
// {{{
.i_clk(i_clk), .i_reset(i_reset),
.i_rx_stb(wbu_rx_stb), .i_rx_data(wbu_rx_data),
.o_wb_cyc(wbu_cyc), .o_wb_stb(wbu_stb),
.o_wb_we(wbu_we),
.o_wb_addr(wbu_tmp_addr),
.o_wb_data(wbu_data),
.i_wb_stall(wbu_stall),
.i_wb_ack(wbu_ack),
.i_wb_data(wbu_idata),
.i_wb_err(wbu_err),
.i_interrupt(w_bus_int),
.o_tx_stb(wbu_tx_stb), .o_tx_data(wbu_tx_data),
.i_tx_busy(wbu_tx_busy),
//
`ifdef SMI_CONSOLE
.i_console_stb(w_console_tx_stb || smi_console_valid),
.i_console_data(smi_console_valid ? smi_console_data[6:0]
: w_console_tx_data),
`else
.i_console_stb(w_console_tx_stb),
.i_console_data(w_console_tx_data),
`endif
.o_console_busy(w_console_busy),
.o_console_stb(w_console_rx_stb),
.o_console_data(w_console_rx_data),
//
.o_dbg(wbubus_dbg[0])
// }}}
);
`ifdef SMI_CONSOLE
assign smi_console_ready = !w_console_busy;
`endif
assign wbu_sel = 4'hf;
assign wbu_addr = wbu_tmp_addr[(27-1):0];
// }}}
// }}}
`else // WBUBUS_MASTER
// {{{
// Null bus master
// {{{
// }}}
// }}}
`endif // WBUBUS_MASTER
`ifdef CFG_ACCESS
// {{{
`ifdef VERILATOR
reg r_cfg_ack;
initial r_cfg_ack = 1'b0;
always @(posedge i_clk)
r_cfg_ack <= wb32_cfg_stb;
assign wb32_cfg_ack = r_cfg_ack;
assign wb32_cfg_stall = 1'b0;
assign wb32_cfg_idata = 32'h00;
assign cfg_debug = 32'h00;
// Verilator lint_off UNUSED
wire cfg_unused;
assign cfg_unused = &{ 1'b0, ICAPE_LGDIV[31:0] };
// Verilator lint_on UNUSED
`else
wbicapetwo #(
.LGDIV(ICAPE_LGDIV)
) u_cfgport(
.i_clk(i_clk),
.i_wb_cyc(wb32_cfg_cyc), .i_wb_stb(wb32_cfg_stb), .i_wb_we(wb32_cfg_we),
.i_wb_addr(wb32_cfg_addr[5-1:0]),
.i_wb_data(wb32_cfg_data), // 32 bits wide
.i_wb_sel(wb32_cfg_sel), // 32/8 bits wide
.o_wb_stall(wb32_cfg_stall),.o_wb_ack(wb32_cfg_ack), .o_wb_data(wb32_cfg_idata),
.o_dbg(cfg_debug)
);
`endif
// }}}
`else // CFG_ACCESS
// {{{
// Null bus slave
// {{{
//
// In the case that there is no wb32_cfg peripheral
// responding on the wb32 bus
assign wb32_cfg_ack = 1'b0;
assign wb32_cfg_err = (wb32_cfg_stb);
assign wb32_cfg_stall = 0;
assign wb32_cfg_idata = 0;
// }}}
// }}}
`endif // CFG_ACCESS
`ifdef GPIO_ACCESS
// {{{
////////////////////////////////////////////////////////////////////////
//
// GPIO
// {{{
// This interface should allow us to control up to 16 GPIO inputs,
// and another 16 GPIO outputs. The interrupt trips when any of
// the inputs changes. (Sorry, which input isn't (yet) selectable.)
//
// Initially set:
// 4x Test points to zero
// SI5324 reset to 0 (active)
// HDMI RX as *not* present
// *TRACE* defaults to OFF
// *ERROR* defaults to NONE (0)
localparam [NGPO-1:0] INITIAL_GPIO = 8'h20;
wbgpio #(
.NIN(NGPI), .NOUT(NGPO), .DEFAULT(INITIAL_GPIO)
) gpioi(
// {{{
i_clk, wb32_gpio_cyc, wb32_gpio_stb, wb32_gpio_we,
wb32_gpio_data, // 32 bits wide
wb32_gpio_sel, // 32/8 bits wide
wb32_gpio_stall, wb32_gpio_ack, wb32_gpio_idata,
i_gpio, o_gpio, gpio_int
// }}}
);
// }}}
// }}}
`else // GPIO_ACCESS
// {{{
// Null interrupt definitions
// {{{
assign gpio_int = 1'b0; // gpio.INT.GPIO.WIRE
// }}}
// }}}
`endif // GPIO_ACCESS
`ifdef SPIO_ACCESS
// {{{
//
// Special purpose I/O driver (buttons, LEDs, and switches)
//
spio #(
.NBTN(5), .NLEDS(8), .NSW(8)
) spioi(
.i_clk(i_clk), .i_reset(i_reset),
.i_wb_cyc(wb32_spio_cyc), .i_wb_stb(wb32_spio_stb), .i_wb_we(wb32_spio_we),
.i_wb_data(wb32_spio_data), // 32 bits wide
.i_wb_sel(wb32_spio_sel), // 32/8 bits wide
.o_wb_stall(wb32_spio_stall),.o_wb_ack(wb32_spio_ack), .o_wb_data(wb32_spio_idata),
.i_sw(i_sw), .i_btn(i_btn), .o_led(w_led),
.o_int(spio_int)
);
assign o_led = w_led;
// }}}
`else // SPIO_ACCESS
// {{{
assign w_btn = 0;
assign o_led = 0;
// Null interrupt definitions
// {{{
assign spio_int = 1'b0; // spio.INT.SPIO.WIRE
// }}}
// }}}
`endif // SPIO_ACCESS
////////////////////////////////////////////////////////////////////////
//
// WBUBUS "wbu_arbiter" master->slave connection
// {{{
wbupsz #(
// {{{
.ADDRESS_WIDTH(22+$clog2(512/8)),
.SMALL_DW(32),
.WIDE_DW(512),
.OPT_LITTLE_ENDIAN(1'b0)
// }}}
) wbu_arbiter_upsz (
// {{{
.i_clk(i_clk),
.i_reset(i_reset),
.i_scyc(wbu_wbu_arbiter_cyc), .i_sstb(wbu_wbu_arbiter_stb), .i_swe(wbu_wbu_arbiter_we),
.i_saddr(wbu_wbu_arbiter_addr[26-1:0]),
.i_sdata(wbu_wbu_arbiter_data), // 32 bits wide
.i_ssel(wbu_wbu_arbiter_sel), // 32/8 bits wide
.o_sstall(wbu_wbu_arbiter_stall),.o_sack(wbu_wbu_arbiter_ack), .o_sdata(wbu_wbu_arbiter_idata), .o_serr(wbu_wbu_arbiter_err),
.o_wcyc(wbwide_wbu_arbiter_cyc), .o_wstb(wbwide_wbu_arbiter_stb), .o_wwe(wbwide_wbu_arbiter_we),
.o_waddr(wbwide_wbu_arbiter_addr[22-1:0]),
.o_wdata(wbwide_wbu_arbiter_data), // 512 bits wide
.o_wsel(wbwide_wbu_arbiter_sel), // 512/8 bits wide
.i_wstall(wbwide_wbu_arbiter_stall), .i_wack(wbwide_wbu_arbiter_ack), .i_wdata(wbwide_wbu_arbiter_idata), .i_werr(wbwide_wbu_arbiter_err)
// }}}
);
// }}}
// }}}
endmodule // main.v
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