358 lines
8.8 KiB
Verilog
358 lines
8.8 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ziptimer.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// Purpose: A lighter weight implementation of the Zip Timer.
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//
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// Interface:
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// Two options:
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// 1. One combined register for both control and value, and ...
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// The reload value is set any time the timer data value is "set".
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// Reading the register returns the timer value. Controls are
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// set so that writing a value to the timer automatically starts
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// it counting down.
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// 2. Two registers, one for control one for value.
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// The control register would have the reload value in it.
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// On the clock when the interface is set to zero the interrupt is set.
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// Hence setting the timer to zero will disable the timer without
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// setting any interrupts. Thus setting it to five will count
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// 5 clocks: 5, 4, 3, 2, 1, Interrupt.
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//
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//
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// Control bits:
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// (Start_n/Stop. This bit has been dropped. Writing to this
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// timer any value but zero starts it. Writing a zero
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// clears and stops it.)
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// AutoReload. If set, then on reset the timer automatically
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// loads the last set value and starts over. This is
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// useful for distinguishing between a one-time interrupt
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// timer, and a repetitive interval timer.
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// (INTEN. Interrupt enable--reaching zero always creates an
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// interrupt, so this control bit isn't needed. The
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// interrupt controller can be used to mask the interrupt.)
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// (COUNT-DOWN/UP: This timer is *only* a count-down timer.
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// There is no means of setting it to count up.)
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// WatchDog
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// This timer can be implemented as a watchdog timer simply by
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// connecting the interrupt line to the reset line of the CPU.
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// When the timer then expires, it will trigger a CPU reset.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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`default_nettype none
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// }}}
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module ziptimer #(
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// {{{
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parameter BW = 32, VW = (BW-1),
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parameter [0:0] RELOADABLE = 1
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// }}}
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) (
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// {{{
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input wire i_clk, i_reset, i_ce,
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// Wishbone inputs
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input wire i_wb_cyc, i_wb_stb, i_wb_we,
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input wire [BW-1:0] i_wb_data,
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input wire [BW/8-1:0] i_wb_sel,
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// Wishbone outputs
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output wire o_wb_stall,
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output reg o_wb_ack,
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output wire [BW-1:0] o_wb_data,
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// Interrupt line
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output reg o_int
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// }}}
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);
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// Local declarations
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// {{{
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reg r_running;
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reg r_zero = 1'b1;
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reg [(VW-1):0] r_value;
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wire wb_write;
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wire auto_reload;
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wire [(VW-1):0] interval_count;
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// }}}
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assign wb_write = ((i_wb_stb)&&(i_wb_we));
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// r_running
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// {{{
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initial r_running = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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r_running <= 1'b0;
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else if (wb_write)
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r_running <= (|i_wb_data[(VW-1):0]);
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else if ((r_zero)&&(!auto_reload))
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r_running <= 1'b0;
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// }}}
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// r_auto_reload, r_interval_count
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// {{{
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generate
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if (RELOADABLE != 0)
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begin : GEN_RELOAD
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// {{{
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reg r_auto_reload;
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reg [(VW-1):0] r_interval_count;
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// r_auto_reload
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// {{{
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initial r_auto_reload = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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r_auto_reload <= 1'b0;
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else if (wb_write)
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r_auto_reload <= (i_wb_data[(BW-1)])
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&&(|i_wb_data[(VW-1):0]);
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// }}}
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assign auto_reload = r_auto_reload;
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// r_interval_count
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// {{{
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// If setting auto-reload mode, and the value to other
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// than zero, set the auto-reload value
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always @(posedge i_clk)
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if (i_reset)
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r_interval_count <= 0;
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else if (wb_write)
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r_interval_count <= i_wb_data[(VW-1):0];
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// }}}
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assign interval_count = r_interval_count;
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// }}}
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end else begin : NO_AUTO_RELOAD
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// {{{
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assign auto_reload = 1'b0;
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assign interval_count = 0;
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// }}}
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end endgenerate
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// }}}
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// r_value
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// {{{
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initial r_value = 0;
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always @(posedge i_clk)
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if (i_reset)
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r_value <= 0;
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else if (wb_write)
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r_value <= i_wb_data[(VW-1):0];
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else if ((i_ce)&&(r_running))
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begin
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if (!r_zero)
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r_value <= r_value - 1'b1;
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else if (auto_reload)
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r_value <= interval_count;
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end
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// }}}
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// r_zero
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// {{{
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always @(posedge i_clk)
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if (i_reset)
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r_zero <= 1'b1;
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else if (wb_write)
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r_zero <= (i_wb_data[(VW-1):0] == 0);
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else if ((r_running)&&(i_ce))
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begin
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if (r_value == { {(VW-1){1'b0}}, 1'b1 })
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r_zero <= 1'b1;
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else if ((r_zero)&&(auto_reload))
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r_zero <= 1'b0;
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end
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// }}}
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// o_int
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// {{{
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// Set the interrupt on our last tick, as we transition from one to
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// zero.
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initial o_int = 1'b0;
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always @(posedge i_clk)
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if ((i_reset)||(wb_write)||(!i_ce))
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o_int <= 1'b0;
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else // if (i_ce)
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o_int <= (r_value == { {(VW-1){1'b0}}, 1'b1 });
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// }}}
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// o_wb_ack
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// {{{
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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o_wb_ack <= (!i_reset)&&(i_wb_stb);
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// }}}
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assign o_wb_stall = 1'b0;
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// o_wb_data
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// {{{
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generate if (VW < BW-1)
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begin : GEN_TRIM
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assign o_wb_data = { auto_reload, {(BW-1-VW){1'b0}}, r_value };
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end else begin : NO_TRIM
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assign o_wb_data = { auto_reload, r_value };
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end endgenerate
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// }}}
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// Make verilator happy
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// {{{
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// verilator coverage_off
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// verilator lint_off UNUSED
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wire unused;
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assign unused = &{ 1'b0, i_wb_cyc, i_wb_data, i_wb_sel };
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// verilator lint_on UNUSED
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// verilator coverage_on
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// }}}
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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// Formal properties
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// {{{
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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`ifdef FORMAL
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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initial assume(i_reset);
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always @(*)
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if (!f_past_valid)
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assume(i_reset);
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always @(posedge i_clk)
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if ((!f_past_valid)||($past(i_reset)))
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begin
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assert(r_value == 0);
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assert(r_running == 0);
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assert(auto_reload == 0);
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assert(r_zero == 1'b1);
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end
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always @(*)
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if (i_wb_stb)
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assume(i_wb_cyc);
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always @(*)
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assert(r_zero == (r_value == 0));
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always @(*)
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if (r_value != 0)
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assert(r_running);
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always @(*)
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if (auto_reload)
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assert(r_running);
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always @(*)
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if (!RELOADABLE)
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assert(auto_reload == 0);
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always @(*)
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if (auto_reload)
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assert(interval_count != 0);
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(r_value)==0)
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&&(!$past(wb_write))&&(!$past(auto_reload)))
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assert(r_value == 0);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&(!$past(wb_write))
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&&($past(r_value)==0)&&($past(auto_reload)))
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begin
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if ($past(i_ce))
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begin
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assert(r_value == interval_count);
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end else
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assert(r_value == $past(r_value));
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end
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))
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&&(!$past(wb_write))&&($past(r_value)!=0))
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begin
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if ($past(i_ce))
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begin
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assert(r_value == $past(r_value)-1'b1);
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end else
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assert(r_value == $past(r_value));
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end
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(wb_write)))
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assert(r_value == $past(i_wb_data[(VW-1):0]));
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// Check auto_reload
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// {{{
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always @(posedge i_clk)
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if (!f_past_valid || $past(i_reset) || !RELOADABLE)
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begin
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assert(!auto_reload);
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end else if ($past(wb_write))
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begin
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if (!$past(i_wb_data[BW-1]))
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begin
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assert(!auto_reload);
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end else
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assert(auto_reload == $past(|i_wb_data[VW-1:0]));
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end else
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assert($stable(auto_reload));
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// }}}
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always @(posedge i_clk)
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if (!(f_past_valid)||($past(i_reset)))
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begin
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assert(!o_int);
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end else if (($past(wb_write))||(!$past(i_ce)))
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begin
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assert(!o_int);
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end else
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assert(o_int == ((r_running)&&(r_value == 0)));
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always @(posedge i_clk)
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if ((!f_past_valid)||($past(i_reset)))
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begin
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assert(!o_wb_ack);
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end else if ($past(i_wb_stb))
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assert(o_wb_ack);
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always @(*)
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assert(!o_wb_stall);
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always @(*)
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assert(o_wb_data[BW-1] == auto_reload);
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always @(*)
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assert(o_wb_data[VW-1:0] == r_value);
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`endif
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// }}}
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endmodule
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