335 lines
9.4 KiB
Verilog
335 lines
9.4 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: zipjiffies.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// Purpose: This peripheral is motivated by the Linux use of 'jiffies'.
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// A process, in Linux, can request to be put to sleep until a certain
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// number of 'jiffies' have elapsed. Using this interface, the CPU can
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// read the number of 'jiffies' from this peripheral (it only has the
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// one location in address space), add the sleep length to it, and
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// write the result back to the peripheral. The zipjiffies peripheral
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// will record the value written to it only if it is nearer the current
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// counter value than the last current waiting interrupt time. If no
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// other interrupts are waiting, and this time is in the future, it will
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// be enabled. (There is currrently no way to disable a jiffie interrupt
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// once set.) The processor may then place this sleep request into a
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// list among other sleep requests. Once the timer expires, it would
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// write the next jiffy request to the peripheral and wake up the process
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// whose timer had expired.
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//
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// Quite elementary, really.
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//
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// Interface:
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// This peripheral contains one register: a counter. Reads from the
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// register return the current value of the counter. Writes within
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// the (N-1) bit space following the current time set an interrupt.
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// Writes of values that occurred in the last 2^(N-1) ticks will be
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// ignored. The timer then interrupts when its value equals that time.
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// Multiple writes cause the jiffies timer to select the nearest possible
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// interrupt. Upon an interrupt, the next interrupt time/value is cleared
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// and will need to be reset if the CPU wants to get notified again. With
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// only the single interface, there is no way of knowing when the next
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// interrupt is scheduled for, neither is there any way to slow down the
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// interrupt timer in case you don't want it overflowing as often and you
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// wish to wait more jiffies than it supports. Thus, currently, if you
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// have a timer you wish to wait upon that is more than 2^31 into the
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// future, you would need to set timers along the way, wake up on those
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// timers, and set further timer's until you finally get to your
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// destination.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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`default_nettype none
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// }}}
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module zipjiffies #(
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parameter BW = 32
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) (
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// {{{
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input wire i_clk, i_reset, i_ce,
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// Wishbone inputs
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input wire i_wb_cyc, i_wb_stb, i_wb_we,
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input wire [(BW-1):0] i_wb_data,
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input wire [BW/8-1:0] i_wb_sel,
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// Wishbone outputs
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output wire o_wb_stall,
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output reg o_wb_ack,
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output wire [(BW-1):0] o_wb_data,
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// Interrupt line
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output reg o_int
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// }}}
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);
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// Local declarations
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// {{{
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reg [(BW-1):0] r_counter;
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//
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reg int_set, new_set, int_now;
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reg [(BW-1):0] int_when, new_when;
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reg signed [(BW-1):0] till_wb, till_when;
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// }}}
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// r_counter
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// {{{
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// Our counter logic: The counter is always counting up--it cannot
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// be stopped or altered. It's really quite simple. Okay, not quite.
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// We still support the clock enable line. We do this in order to
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// support debugging, so that if we get everything running inside a
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// debugger, the timer's all slow down so that everything can be stepped
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// together, one clock at a time.
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//
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initial r_counter = 0;
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always @(posedge i_clk)
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if (i_reset)
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r_counter <= 0;
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else if (i_ce)
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r_counter <= r_counter+1;
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// }}}
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// int_now
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// {{{
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initial int_now = 0;
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always @(posedge i_clk)
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if (i_reset)
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int_now <= 0;
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else if (i_ce)
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int_now <= ((r_counter + 1) == (int_when));
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else
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int_now <= 1'b0;
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// }}}
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// new_set, new_when
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// {{{
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// Writes to the counter set an interrupt--but only if they are in the
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// future as determined by the signed result of an unsigned subtract.
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//
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// assign till_when = int_when-r_counter;
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// assign till_wb = new_when-r_counter;
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initial new_set = 1'b0;
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always @(posedge i_clk)
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begin
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// Delay WB commands (writes) by a clock to simplify our logic
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new_set <= (i_wb_stb && i_wb_we);
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// new_when is a don't care when new_set = 0, so don't worry
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// about setting it at all times.
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new_when<= i_wb_data;
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till_wb <= (i_wb_data - r_counter - (i_ce ? 1:0));
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till_when <= (int_when - i_wb_data);
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if (i_reset)
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new_set <= 1'b0;
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end
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// }}}
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// o_int, int_set
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// {{{
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initial o_int = 1'b0;
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initial int_set = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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begin
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// {{{
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o_int <= 0;
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int_set <= 0;
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// }}}
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end else begin
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// {{{
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o_int <= 1'b0;
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if ((i_ce)&&(int_set)&&(r_counter == int_when))
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// Interrupts are self-clearing
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o_int <= 1'b1; // Set the interrupt flag for one clock
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else if ((new_set)&&(till_wb <= 0))
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o_int <= 1'b1;
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if ((new_set)&&(till_wb > 0))
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int_set <= 1'b1;
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else if (int_now)
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int_set <= 1'b0;
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// }}}
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end
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// }}}
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// int_when
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// {{{
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always @(posedge i_clk)
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if ((new_set)&&(till_wb > 0)&&((till_when[BW-1])||(!int_set)))
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int_when <= new_when;
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// }}}
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// o_wb_ack
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// {{{
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// Acknowledge any wishbone accesses -- everything we did took only
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// one clock anyway.
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//
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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o_wb_ack <= 1'b0;
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else
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o_wb_ack <= i_wb_stb;
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// }}}
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assign o_wb_data = r_counter;
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assign o_wb_stall = 1'b0;
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// Make verilator happy
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// {{{
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// verilator coverage_off
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// verilator lint_off UNUSED
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wire unused;
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assign unused = &{ 1'b0, i_wb_cyc, i_wb_sel };
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// verilator lint_on UNUSED
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// verilator coverage_on
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// }}}
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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// Formal properties
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// {{{
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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`ifdef FORMAL
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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////////////////////////////////////////////////////////////////////////
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//
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// Assumptions about our inputs
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// {{{
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////////////////////////////////////////////////////////////////////////
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//
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//
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// One basic WB assumtion
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// Anytime the stb is high, the cycle line must also be high
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always @(posedge i_clk)
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assume((!i_wb_stb)||(i_wb_cyc));
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// }}}
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////////////////////////////////////////////////////////////////////////
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//
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// Assertions about our bus outputs
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// {{{
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////////////////////////////////////////////////////////////////////////
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//
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//
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// We never stall the bus
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always @(*)
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assert(!o_wb_stall);
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// We always ack every transaction on the following clock
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb)))
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begin
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assert(o_wb_ack);
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end else
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assert(!o_wb_ack);
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// }}}
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///////////////////////////////////////////////////////////////////////
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//
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// Assumptions about our internal state and our outputs
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// {{{
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////////////////////////////////////////////////////////////////////////
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//
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//
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_reset)))
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begin
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assert(!o_wb_ack);
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end
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb))
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&&($past(i_wb_we)))
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assert(new_when == $past(i_wb_data));
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb))
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&&($past(i_wb_we)))
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begin
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assert(new_set);
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end else
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assert(!new_set);
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//
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//
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//
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_reset)))
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assert(!o_int);
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_reset)))
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begin
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assert(!int_set);
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assert(!new_set);
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end
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(new_set))
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&&(!$past(till_wb[BW-1]))
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&&($past(till_wb) > 0))
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assert(int_set);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_ce))
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&&($past(r_counter)==$past(int_when)))
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begin
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assert((o_int)||(!$past(int_set)));
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// assert((!int_set)||($past(new_set))); // !!!!!
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end
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&(!$past(new_set))&&(!$past(int_set)))
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assert(!int_set);
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always @(posedge i_clk)
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if ((!f_past_valid)||($past(i_reset)))
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begin
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assert(!o_int);
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end else if (($past(new_set))&&($past(till_wb) < 0))
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assert(o_int);
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always @(posedge i_clk)
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if ((f_past_valid)&&
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((!$past(new_set))
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||($past(till_wb[BW-1]))
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||($past(till_wb == 0))))
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assert(int_when == $past(int_when));
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// }}}
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`endif
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// }}}
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endmodule
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