441 lines
12 KiB
Verilog
441 lines
12 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: zipdma.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// Purpose: (Upgraded) Wishbone DMA controller for the ZipCPU
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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`default_nettype none
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// }}}
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module zipdma #(
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// {{{
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parameter ADDRESS_WIDTH=30, LGMEMLEN = 10,
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parameter LGDMALENGTH=ADDRESS_WIDTH,
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parameter SLV_WIDTH=32,
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parameter BUS_WIDTH=512,
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parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0,
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parameter [0:0] OPT_LOWPOWER = 1'b0,
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parameter [0:0] OPT_REGISTER_RAM = 1'b0,
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localparam AW=ADDRESS_WIDTH-$clog2(BUS_WIDTH/8)
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// }}}
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) (
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// {{{
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input wire i_clk, i_reset,
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// Slave port
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// {{{
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// Slave/control wishbone inputs
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input wire i_swb_cyc, i_swb_stb, i_swb_we,
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input wire [1:0] i_swb_addr,
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input wire [SLV_WIDTH-1:0] i_swb_data,
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input wire [SLV_WIDTH/8-1:0] i_swb_sel,
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// Slave/control wishbone outputs
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output wire o_swb_stall,
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output wire o_swb_ack,
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output wire [SLV_WIDTH-1:0] o_swb_data,
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// }}}
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// Master/DMA port
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// {{{
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output wire o_mwb_cyc, o_mwb_stb, o_mwb_we,
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output wire [AW-1:0] o_mwb_addr,
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output wire [BUS_WIDTH-1:0] o_mwb_data,
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output wire [BUS_WIDTH/8-1:0] o_mwb_sel,
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// Master/DMA wishbone responses from the bus
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input wire i_mwb_stall, i_mwb_ack,
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input wire [BUS_WIDTH-1:0] i_mwb_data,
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input wire i_mwb_err,
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// }}}
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// The interrupt device interrupt lines
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input wire [31:0] i_dev_ints,
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// An interrupt to be set upon completion
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output wire o_interrupt
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// }}}
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);
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// Local declarations
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// {{{
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localparam FIFO_WIDTH = BUS_WIDTH+$clog2(BUS_WIDTH/8)+2;
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localparam LGFIFO = LGMEMLEN-$clog2(BUS_WIDTH/8);
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wire dma_request, dma_abort,
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dma_busy, dma_err;
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wire [ADDRESS_WIDTH-1:0] dma_src, dma_dst,
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read_addr, write_addr;
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wire [LGDMALENGTH-1:0] dma_length, remaining_len;
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wire [LGMEMLEN:0] dma_transferlen;
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wire dma_trigger;
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wire mm2s_request, s2mm_request;
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wire mm2s_busy, s2mm_busy;
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wire mm2s_err, s2mm_err;
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wire mm2s_inc, s2mm_inc;
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wire [1:0] mm2s_size, s2mm_size;
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wire [ADDRESS_WIDTH-1:0] mm2s_addr, s2mm_addr;
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wire [LGMEMLEN:0] mm2s_transferlen, s2mm_transferlen;
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wire mm2s_rd_cyc, mm2s_rd_stb, mm2s_rd_we,
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mm2s_rd_stall, mm2s_rd_ack, mm2s_rd_err;
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wire [AW-1:0] mm2s_rd_addr;
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wire [BUS_WIDTH-1:0] mm2s_rd_data;
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wire [BUS_WIDTH/8-1:0] mm2s_rd_sel;
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wire mm2s_valid, mm2s_ready, mm2s_last;
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wire [BUS_WIDTH-1:0] mm2s_data;
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wire [$clog2(BUS_WIDTH/8):0] mm2s_bytes;
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wire rx_valid, rx_ready, rx_last;
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wire [BUS_WIDTH-1:0] rx_data;
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wire [$clog2(BUS_WIDTH/8):0] rx_bytes;
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wire tx_valid, tx_ready, tx_last;
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wire [BUS_WIDTH-1:0] tx_data;
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wire [$clog2(BUS_WIDTH/8):0] tx_bytes;
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wire sfifo_full, sfifo_empty;
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wire [LGFIFO:0] ign_sfifo_fill;
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wire s2mm_valid, s2mm_ready, s2mm_last;
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wire [BUS_WIDTH-1:0] s2mm_data;
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wire [$clog2(BUS_WIDTH/8):0] s2mm_bytes;
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wire s2mm_wr_cyc, s2mm_wr_stb, s2mm_wr_we,
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s2mm_wr_stall, s2mm_wr_ack, s2mm_wr_err;
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wire [AW-1:0] s2mm_wr_addr;
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wire [BUS_WIDTH-1:0] s2mm_wr_data;
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wire [BUS_WIDTH/8-1:0] s2mm_wr_sel;
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wire wb_cyc, wb_stb, wb_we,
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wb_stall, wb_ack, wb_err;
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wire [AW-1:0] wb_addr;
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wire [BUS_WIDTH-1:0] wb_data, wb_idata;
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wire [BUS_WIDTH/8-1:0] wb_sel;
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// }}}
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zipdma_ctrl #(
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// {{{
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.ADDRESS_WIDTH(ADDRESS_WIDTH),
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.LGMEMLEN(LGMEMLEN),
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.LGDMALENGTH(ADDRESS_WIDTH),
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.OPT_LOWPOWER(OPT_LOWPOWER)
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// }}}
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) u_controller (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset),
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// Slave WB control port
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// {{{
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// Slave/control wishbone inputs
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.i_cyc(i_swb_cyc), .i_stb(i_swb_stb), .i_we(i_swb_we),
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.i_addr(i_swb_addr),
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.i_data(i_swb_data), .i_sel(i_swb_sel),
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// Slave/control wishbone outputs
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.o_stall(o_swb_stall),
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.o_ack(o_swb_ack), .o_data(o_swb_data),
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// }}}
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// Internal DMA controls
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// {{{
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.o_dma_request(dma_request), .o_dma_abort(dma_abort),
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.i_dma_busy(dma_busy), .i_dma_err(dma_err),
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.o_src_addr(dma_src), .o_dst_addr(dma_dst),
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.o_length(dma_length), .o_transferlen(dma_transferlen),
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.o_mm2s_inc(mm2s_inc), .o_mm2s_size(mm2s_size),
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.o_s2mm_inc(s2mm_inc), .o_s2mm_size(s2mm_size),
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//
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.o_trigger(dma_trigger),
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//
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.i_current_src(read_addr),
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.i_current_dst(write_addr),
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.i_remaining_len(remaining_len),
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// }}}
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.i_dma_int(i_dev_ints), .o_interrupt(o_interrupt)
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// }}}
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);
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zipdma_fsm #(
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// {{{
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.ADDRESS_WIDTH(ADDRESS_WIDTH),
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.LGDMALENGTH(ADDRESS_WIDTH),
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.LGSUBLENGTH(LGMEMLEN)
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// }}}
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) u_dma_fsm (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset),
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.i_soft_reset(dma_abort),
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// DMA control
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// {{{
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.i_dma_request(dma_request),
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.o_dma_busy(dma_busy), .o_dma_err(dma_err),
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.i_src_addr(dma_src), .i_dst_addr(dma_dst),
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.i_length(dma_length), .i_transferlen(dma_transferlen),
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.i_trigger(dma_trigger),
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.o_remaining_len(remaining_len),
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// }}}
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// Downstream MM2S configuration
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// {{{
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.o_mm2s_request(mm2s_request),
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.i_mm2s_busy(mm2s_busy),
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.i_mm2s_err(mm2s_err),
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.i_mm2s_inc(mm2s_inc),
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.o_mm2s_addr(mm2s_addr),
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.o_mm2s_transferlen(mm2s_transferlen),
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// }}}
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// Downstream S2MM configuration
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// {{{
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.o_s2mm_request(s2mm_request),
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.i_s2mm_busy(s2mm_busy),
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.i_s2mm_err(s2mm_err),
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.i_s2mm_inc(s2mm_inc),
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.o_s2mm_addr(s2mm_addr),
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.o_s2mm_transferlen(s2mm_transferlen)
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// }}}
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// }}}
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);
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zipdma_mm2s #(
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// {{{
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.ADDRESS_WIDTH(ADDRESS_WIDTH),
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.BUS_WIDTH(BUS_WIDTH),
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.LGLENGTH(LGMEMLEN),
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.OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN),
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.OPT_LOWPOWER(OPT_LOWPOWER)
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// }}}
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) u_mm2s (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset || dma_abort),
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// DMA control
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// {{{
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.i_request(mm2s_request),
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.o_busy(mm2s_busy), .o_err(mm2s_err),
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.i_inc(mm2s_inc), .i_size(mm2s_size),
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.i_transferlen(mm2s_transferlen),
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.i_addr(mm2s_addr),
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// }}}
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// Wishbone master interface
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// {{{
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.o_rd_cyc(mm2s_rd_cyc),
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.o_rd_stb(mm2s_rd_stb),
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.o_rd_we(mm2s_rd_we),
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.o_rd_addr(mm2s_rd_addr),
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.o_rd_data(mm2s_rd_data),
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.o_rd_sel(mm2s_rd_sel),
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//
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.i_rd_stall(mm2s_rd_stall),
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.i_rd_ack(mm2s_rd_ack),
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.i_rd_data(wb_idata),
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.i_rd_err(mm2s_rd_err),
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// }}}
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// MM2S Stream interface
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// {{{
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.M_VALID(mm2s_valid),
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.M_READY(mm2s_ready),
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.M_DATA(mm2s_data),
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.M_BYTES(mm2s_bytes),
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.M_LAST(mm2s_last)
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// }}}
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// }}}
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);
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zipdma_rxgears #(
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// {{{
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.BUS_WIDTH(BUS_WIDTH),
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.OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN)
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// }}}
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) u_rxgears (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset), .i_soft_reset(dma_abort),
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//
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.S_VALID(mm2s_valid), .S_READY(mm2s_ready),
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.S_DATA(mm2s_data), .S_BYTES(mm2s_bytes),
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.S_LAST(mm2s_last),
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//
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.M_VALID(rx_valid), .M_READY(rx_ready),
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.M_DATA(rx_data), .M_BYTES(rx_bytes),
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.M_LAST(rx_last)
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// }}}
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);
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sfifo #(
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// {{{
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.BW(FIFO_WIDTH),
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.LGFLEN(LGFIFO),
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.OPT_ASYNC_READ(!OPT_REGISTER_RAM),
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.OPT_WRITE_ON_FULL(1'b0),
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.OPT_READ_ON_EMPTY(1'b0)
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// }}}
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) u_sfifo (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset || dma_abort),
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//
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.i_wr(rx_valid), .i_data({ rx_last, rx_bytes, rx_data }),
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.o_full(sfifo_full), .o_fill(ign_sfifo_fill),
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//
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.i_rd(tx_ready), .o_data({ tx_last, tx_bytes, tx_data }),
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.o_empty(sfifo_empty)
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// }}}
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);
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assign rx_ready = !sfifo_full;
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assign tx_valid = !sfifo_empty;
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zipdma_txgears #(
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// {{{
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.BUS_WIDTH(BUS_WIDTH),
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.OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN)
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// }}}
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) u_txgears (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset),
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.i_soft_reset(dma_abort), .i_size(s2mm_size),
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// Incoming stream
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// {{{
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.S_VALID(tx_valid), .S_READY(tx_ready),
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.S_DATA(tx_data), .S_BYTES(tx_bytes),
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.S_LAST(tx_last),
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// }}}
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// Outgoing stream to S2MM
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// {{{
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.M_VALID(s2mm_valid), .M_READY(s2mm_ready),
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.M_DATA(s2mm_data), .M_BYTES(s2mm_bytes),
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.M_LAST(s2mm_last)
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// }}}
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// }}}
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);
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zipdma_s2mm #(
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// {{{
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.ADDRESS_WIDTH(ADDRESS_WIDTH),
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.BUS_WIDTH(BUS_WIDTH),
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.OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN),
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.LGPIPE(LGMEMLEN)
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// }}}
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) u_s2mm (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset || dma_abort),
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// S2MM configuration
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// {{{
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.i_request(s2mm_request),
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.o_busy(s2mm_busy), .o_err(s2mm_err),
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.i_inc(s2mm_inc), .i_size(s2mm_size),
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.i_addr(s2mm_addr),
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// }}}
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// Stream data source
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// {{{
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.S_VALID(s2mm_valid), .S_READY(s2mm_ready),
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.S_DATA(s2mm_data), .S_BYTES(s2mm_bytes),
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.S_LAST(s2mm_last),
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// }}}
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// Outgoing Wishbone interface
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// {{{
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.o_wr_cyc(s2mm_wr_cyc),
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.o_wr_stb(s2mm_wr_stb),
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.o_wr_we(s2mm_wr_we),
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.o_wr_addr(s2mm_wr_addr),
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.o_wr_data(s2mm_wr_data),
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.o_wr_sel(s2mm_wr_sel),
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//
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.i_wr_stall(s2mm_wr_stall),
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.i_wr_ack(s2mm_wr_ack),
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.i_wr_data(wb_idata),
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.i_wr_err(s2mm_wr_err)
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// }}}
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// }}}
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);
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wbarbiter #(
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// {{{
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.DW(BUS_WIDTH), .AW(AW), .OPT_ZERO_ON_IDLE(OPT_LOWPOWER)
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// }}}
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) u_arbiter (
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// {{{
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.i_clk(i_clk), .i_reset(i_reset),
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//
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.i_a_cyc(mm2s_rd_cyc), .i_a_stb(mm2s_rd_stb),
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.i_a_we(mm2s_rd_we), .i_a_adr(mm2s_rd_addr),
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.i_a_dat((OPT_LOWPOWER) ? mm2s_rd_data : s2mm_wr_data),
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.i_a_sel(mm2s_rd_sel),
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.o_a_stall(mm2s_rd_stall), .o_a_ack(mm2s_rd_ack),
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.o_a_err(mm2s_rd_err),
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//
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.i_b_cyc(s2mm_wr_cyc), .i_b_stb(s2mm_wr_stb),
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.i_b_we(s2mm_wr_we), .i_b_adr(s2mm_wr_addr),
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.i_b_dat(s2mm_wr_data), .i_b_sel(s2mm_wr_sel),
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.o_b_stall(s2mm_wr_stall), .o_b_ack(s2mm_wr_ack),
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.o_b_err(s2mm_wr_err),
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//
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.o_cyc(wb_cyc), .o_stb(wb_stb),
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.o_we(wb_we), .o_adr(wb_addr),
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.o_dat(wb_data), .o_sel(wb_sel),
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.i_stall(wb_stall), .i_ack(wb_ack),
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.i_err(wb_err)
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// }}}
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);
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assign o_mwb_cyc = wb_cyc;
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assign o_mwb_stb = wb_stb;
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assign o_mwb_we = wb_we;
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assign o_mwb_addr = wb_addr;
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assign o_mwb_data = wb_data;
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assign o_mwb_sel = wb_sel;
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assign wb_stall = i_mwb_stall;
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assign wb_ack = i_mwb_ack;
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assign wb_idata = i_mwb_data;
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assign wb_err = i_mwb_err;
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assign read_addr = { mm2s_rd_addr, {($clog2(BUS_WIDTH/8)){1'b0}} };
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assign write_addr = { s2mm_wr_addr, {($clog2(BUS_WIDTH/8)){1'b0}} };
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// Make verilator happy
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// {{{
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// verilator lint_off UNUSED
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wire unused;
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assign unused = &{ 1'b0, ign_sfifo_fill, mm2s_rd_data, rx_ready,
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s2mm_transferlen };
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// verilator lint_on UNUSED
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// }}}
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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// Formal properties
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// {{{
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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`ifdef FORMAL
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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always @(*)
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if (!f_past_valid)
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assume(i_reset);
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`endif
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// }}}
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endmodule
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