62 lines
2.0 KiB
Verilog
62 lines
2.0 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ./iscachable.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// DO NOT EDIT THIS FILE!
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// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
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// DO NOT EDIT THIS FILE!
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//
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// CmdLine: autofpga autofpga -I .: -d -o . allclocks.txt global.txt wbdown.txt icape.txt version.txt gpio.txt spio.txt wbuconsole.txt zipmaster.txt bkram.txt ddr3.txt sdio.txt emmc.txt sdioscope.txt emmcscope.txt mem_bkram_only.txt mem_flash_bkram.txt i2ccpu.txt fan.txt sirefclk.txt i2cscope.txt
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, files
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// }}}
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`default_nettype none
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//
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module iscachable(
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// {{{
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input wire [28-1:0] i_addr,
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output reg o_cachable
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// }}}
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);
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always @(*)
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begin
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o_cachable = 1'b0;
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// Bus master: wbwide
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// Bus master: wb32
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// Bus master: wb32_sio
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// bkram
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if ((i_addr[27:0] & 28'he000000) == 28'h4000000)
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o_cachable = 1'b1;
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// ddr3_controller
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if ((i_addr[27:0] & 28'h8000000) == 28'h8000000)
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o_cachable = 1'b1;
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end
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endmodule
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