612 lines
17 KiB
Verilog
612 lines
17 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: div.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// Purpose: Provide an Integer divide capability to the Zip CPU. Provides
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// for both signed and unsigned divide.
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//
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// Steps:
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// i_reset The DIVide unit starts in idle. It can also be placed into an
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// idle by asserting the reset input.
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//
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// i_wr When i_reset is asserted, a divide begins. On the next clock:
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//
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// o_busy is set high so everyone else knows we are at work and they can
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// wait for us to complete.
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//
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// pre_sign is set to true if we need to do a signed divide. In this
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// case, we take a clock cycle to turn the divide into an unsigned
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// divide.
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//
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// o_quotient, a place to store our result, is initialized to all zeros.
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//
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// r_dividend is set to the numerator
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//
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// r_divisor is set to 2^31 * the denominator (shift left by 31, or add
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// 31 zeros to the right of the number.
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//
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// pre_sign When true (clock cycle after i_wr), a clock cycle is used
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// to take the absolute value of the various arguments (r_dividend
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// and r_divisor), and to calculate what sign the output result
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// should be.
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//
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//
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// At this point, the divide is has started. The divide works by walking
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// through every shift of the
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//
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// DIVIDEND over the
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// DIVISOR
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//
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// If the DIVISOR is bigger than the dividend, the divisor is shifted
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// right, and nothing is done to the output quotient.
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//
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// DIVIDEND
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// DIVISOR
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//
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// This repeats, until DIVISOR is less than or equal to the divident, as in
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//
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// DIVIDEND
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// DIVISOR
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//
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// At this point, if the DIVISOR is less than the dividend, the
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// divisor is subtracted from the dividend, and the DIVISOR is again
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// shifted to the right. Further, a '1' bit gets set in the output
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// quotient.
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//
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// Once we've done this for 32 clocks, we've accumulated our answer into
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// the output quotient, and we can proceed to the next step. If the
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// result will be signed, the next step negates the quotient, otherwise
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// it returns the result.
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//
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// On the clock when we are done, o_busy is set to false, and o_valid set
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// to true. (It is a violation of the ZipCPU internal protocol for both
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// busy and valid to ever be true on the same clock. It is also a
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// violation for busy to be false with valid true thereafter.)
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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`default_nettype none
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// }}}
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module div #(
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parameter BW=32, LGBW = 5,
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parameter [0:0] OPT_LOWPOWER = 1'b0
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) (
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// {{{
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input wire i_clk, i_reset,
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// Input parameters
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input wire i_wr, i_signed,
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input wire [(BW-1):0] i_numerator, i_denominator,
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// Output parameters
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output reg o_busy, o_valid, o_err,
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output reg [(BW-1):0] o_quotient,
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output wire [3:0] o_flags
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// }}}
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);
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// Local declarations
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// {{{
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// r_busy is an internal busy register. It will clear one clock
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// before we are valid, so it can't be o_busy ...
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//
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reg r_busy;
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reg [BW-1:0] r_divisor;
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reg [(2*BW-2):0] r_dividend;
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wire [(BW):0] diff; // , xdiff[(BW-1):0];
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assign diff = r_dividend[2*BW-2:BW-1] - r_divisor;
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reg r_sign, pre_sign, r_z, r_c, last_bit;
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reg [(LGBW-1):0] r_bit;
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reg zero_divisor;
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wire w_n;
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// }}}
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// r_busy
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// {{{
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// The Divide logic begins with r_busy. We use r_busy to determine
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// whether or not the divide is in progress, vs being complete.
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// Here, we clear r_busy on any reset and set it on i_wr (the request
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// to do a divide). The divide ends when we are on the last bit,
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// or equivalently when we discover we are dividing by zero.
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initial r_busy = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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r_busy <= 1'b0;
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else if (i_wr)
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r_busy <= 1'b1;
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else if ((last_bit)||(zero_divisor))
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r_busy <= 1'b0;
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// }}}
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// o_busy
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// {{{
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// o_busy is very similar to r_busy, save for some key differences.
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// Primary among them is that o_busy needs to (possibly) be true
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// for an extra clock after r_busy clears. This would be that extra
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// clock where we negate the result (assuming a signed divide, and that
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// the result is supposed to be negative.) Otherwise, the two are
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// identical.
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initial o_busy = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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o_busy <= 1'b0;
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else if (i_wr)
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o_busy <= 1'b1;
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else if (((last_bit)&&(!r_sign))||(zero_divisor))
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o_busy <= 1'b0;
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else if (!r_busy)
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o_busy <= 1'b0;
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// }}}
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// zero_divisor
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// {{{
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always @(posedge i_clk)
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if (i_wr)
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zero_divisor <= (i_denominator == 0);
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// }}}
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// o_valid
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// {{{
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// o_valid is part of the ZipCPU protocol. It will be set to true
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// anytime our answer is valid and may be used by the calling module.
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// Indeed, the ZipCPU will halt (and ignore us) once the i_wr has been
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// set until o_valid gets set.
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//
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// Here, we clear o_valid on a reset, and any time we are on the last
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// bit while busy (provided the sign is zero, or we are dividing by
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// zero). Since o_valid is self-clearing, we don't need to clear
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// it on an i_wr signal.
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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if ((i_reset)||(o_valid))
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o_valid <= 1'b0;
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else if ((r_busy)&&(zero_divisor))
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o_valid <= 1'b1;
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else if (r_busy)
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begin
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if (last_bit)
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o_valid <= (!r_sign);
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end else if (r_sign)
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begin
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o_valid <= 1'b1;
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end else
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o_valid <= 1'b0;
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// }}}
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// o_err
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// {{{
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// Division by zero error reporting. Anytime we detect a zero divisor,
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// we set our output error, and then hold it until we are valid and
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// everything clears.
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initial o_err = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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o_err <= 1'b0;
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else if ((r_busy)&&(zero_divisor))
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o_err <= 1'b1;
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else
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o_err <= 1'b0;
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// }}}
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// r_bit
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// {{{
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// Keep track of which "bit" of our divide we are on. This number
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// ranges from 31 down to zero. On any write, we set ourselves to
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// 5'h1f. Otherwise, while we are busy (but not within the pre-sign
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// adjustment stage), we subtract one from our value on every clock.
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initial r_bit = 0;
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always @(posedge i_clk)
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if (i_reset)
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r_bit <= 0;
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else if ((r_busy)&&(!pre_sign))
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r_bit <= r_bit + 1'b1;
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else
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r_bit <= 0;
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// }}}
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// last_bit
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// {{{
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// This logic replaces a lot of logic that was inside our giant state
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// machine with ... something simpler. In particular, we'll use this
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// logic to determine if we are processing our last bit. The only trick
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// is, this bit needs to be set whenever (r_busy) and (r_bit == -1),
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// hence we need to set on (r_busy) and (r_bit == -2) so as to be set
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// when (r_bit == 0).
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initial last_bit = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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last_bit <= 1'b0;
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else if (r_busy)
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last_bit <= (r_bit == {(LGBW){1'b1}}-1'b1);
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else
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last_bit <= 1'b0;
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// }}}
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// pre_sign
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// {{{
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// This is part of the state machine. pre_sign indicates that we need
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// a extra clock to take the absolute value of our inputs. It need only
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// be true for the one clock, and then it must clear itself.
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initial pre_sign = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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pre_sign <= 1'b0;
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else
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pre_sign <= (i_wr)&&(i_signed)&&((i_numerator[BW-1])||(i_denominator[BW-1]));
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// }}}
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// r_z
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// {{{
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// As a result of our operation, we need to set the flags. The most
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// difficult of these is the "Z" flag indicating that the result is
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// zero. Here, we'll use the same logic that sets the low-order
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// bit to clear our zero flag, and leave the zero flag set in all
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// other cases.
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always @(posedge i_clk)
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if (i_wr)
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r_z <= 1'b1;
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else if ((r_busy)&&(!pre_sign)&&(!diff[BW]))
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r_z <= 1'b0;
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// }}}
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// r_dividend
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// {{{
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// This is initially the numerator. On a signed divide, it then becomes
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// the absolute value of the numerator. We'll subtract from this value
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// the divisor for every output bit we are looking for--just as with
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// traditional long division.
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always @(posedge i_clk)
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if (pre_sign)
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begin
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// If we are doing a signed divide, then take the
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// absolute value of the dividend
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if (r_dividend[BW-1])
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begin
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r_dividend[2*BW-2:0] <= {(2*BW-1){1'b0}};
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r_dividend[BW:0] <= -{ 1'b1, r_dividend[BW-1:0] };
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end
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end else if (r_busy)
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begin
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r_dividend <= { r_dividend[2*BW-3:0], 1'b0 };
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if (!diff[BW])
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r_dividend[2*BW-2:BW] <= diff[(BW-2):0];
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end else if (!r_busy && (!OPT_LOWPOWER || i_wr))
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// Once we are done, and r_busy is no longer high, we'll
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// always accept new values into our dividend. This
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// guarantees that, when i_wr is set, the new value
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// is already set as desired.
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r_dividend <= { 31'h0, i_numerator };
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// }}}
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// r_divisor
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// {{{
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initial r_divisor = 0;
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always @(posedge i_clk)
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if (i_reset)
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r_divisor <= 0;
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else if ((pre_sign)&&(r_busy))
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begin
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if (r_divisor[BW-1])
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r_divisor <= -r_divisor;
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end else if (!r_busy && (!OPT_LOWPOWER || i_wr))
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r_divisor <= i_denominator;
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// }}}
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// r_sign
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// {{{
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// is a flag for our state machine control(s). r_sign will be set to
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// true any time we are doing a signed divide and the result must be
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// negative. In that case, we take a final logic stage at the end of
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// the divide to negate the output. This flag is what tells us we need
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// to do that. r_busy will be true during the divide, then when r_busy
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// goes low, r_sign will be checked, then the idle/reset stage will have
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// been reached. For this reason, we cannot set r_sign unless we are
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// up to something.
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initial r_sign = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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r_sign <= 1'b0;
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else if (pre_sign)
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r_sign <= ((r_divisor[(BW-1)])^(r_dividend[(BW-1)]));
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else if (r_busy)
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r_sign <= (r_sign)&&(!zero_divisor);
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else
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r_sign <= 1'b0;
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// }}}
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// o_quotient
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// {{{
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initial o_quotient = 0;
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always @(posedge i_clk)
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if (i_reset)
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o_quotient <= 0;
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else if (r_busy)
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begin
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o_quotient <= { o_quotient[(BW-2):0], 1'b0 };
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if (!diff[BW])
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o_quotient[0] <= 1'b1;
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end else if (r_sign)
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o_quotient <= -o_quotient;
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else
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o_quotient <= 0;
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// }}}
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// r_c
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// {{{
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// Set Carry on an exact divide
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// Perhaps nothing uses this, but ... well, I suppose we could remove
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// this logic eventually, just ... not yet.
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initial r_c = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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r_c <= 1'b0;
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else
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r_c <= (r_busy)&&(diff == 0);
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// }}}
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// w_n
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// {{{
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// The last flag: Negative. This flag is set assuming that the result
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// of the divide was negative (i.e., the high order bit is set). This
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// will also be true of an unsigned divide--if the high order bit is
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// ever set upon completion. Indeed, you might argue that there's no
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// logic involved.
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assign w_n = o_quotient[(BW-1)];
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// }}}
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assign o_flags = { 1'b0, w_n, r_c, r_z };
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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// Formal properties
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// {{{
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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`ifdef FORMAL
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reg f_past_valid;
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initial f_past_valid = 0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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`ifdef DIV
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`define ASSUME assume
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`else
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`define ASSUME assert
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`endif
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initial `ASSUME(i_reset);
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always @(*)
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if (!f_past_valid)
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`ASSUME(i_reset);
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always @(posedge i_clk)
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if ((!f_past_valid)||($past(i_reset)))
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begin
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assert(!o_busy);
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assert(!o_valid);
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assert(!o_err);
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//
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assert(!r_busy);
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// assert(!zero_divisor);
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assert(r_bit==0);
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assert(!last_bit);
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assert(!pre_sign);
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// assert(!r_z);
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// assert(r_dividend==0);
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assert(o_quotient==0);
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assert(!r_c);
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assert(r_divisor==0);
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`ASSUME(!i_wr);
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end
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always @(*)
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if (o_busy)
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`ASSUME(!i_wr);
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always @(*)
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if (r_busy)
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assert(o_busy);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(o_busy))&&(!o_busy))
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begin
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assert(o_valid);
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end
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// A formal methods section
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//
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// This section isn't yet complete. For now, it is just
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// a description of things I think should be in here ... not
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// yet a description of what it would take to prove
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// this divide (yet).
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always @(*)
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if (o_err)
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assert(o_valid);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_wr)))
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assert(!pre_sign);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr))&&($past(i_signed))
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&&(|$past({i_numerator[BW-1],i_denominator[BW-1]})))
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assert(pre_sign);
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// always @(posedge i_clk)
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// if ((f_past_valid)&&(!$past(pre_sign)))
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// assert(!r_sign);
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reg [BW:0] f_bits_set;
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr)))
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assert(o_busy);
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(o_valid)))
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assert(!o_valid);
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always @(*)
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if ((o_valid)&&(!o_err))
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begin
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assert(r_z == ((o_quotient == 0)? 1'b1:1'b0));
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end else if (o_busy)
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assert(r_z == (((o_quotient&f_bits_set[BW-1:0]) == 0)? 1'b1: 1'b0));
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always @(*)
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if ((o_valid)&&(!o_err))
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assert(w_n == o_quotient[BW-1]);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(r_busy))&&(!$past(i_wr)))
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assert(!o_busy);
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always @(posedge i_clk)
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assert((!o_busy)||(!o_valid));
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always @(*)
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if(r_busy)
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assert(o_busy);
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always @(posedge i_clk)
|
|
if (i_reset)
|
|
f_bits_set <= 0;
|
|
else if (i_wr)
|
|
f_bits_set <= 0;
|
|
else if ((r_busy)&&(!pre_sign))
|
|
f_bits_set <= { f_bits_set[BW-1:0], 1'b1 };
|
|
|
|
always @(posedge i_clk)
|
|
if (r_busy)
|
|
assert(((1<<r_bit)-1) == f_bits_set);
|
|
|
|
always @(*)
|
|
if ((o_valid)&&(!o_err))
|
|
assert((!f_bits_set[BW])&&(&f_bits_set[BW-1:0]));
|
|
|
|
|
|
/*
|
|
always @(posedge i_clk)
|
|
if ((f_past_valid)&&(!$past(i_reset))&&($past(r_busy))
|
|
&&($past(r_divisor[2*BW-2:BW])==0))
|
|
begin
|
|
if ($past(r_divisor) == 0)
|
|
begin
|
|
assert(o_err);
|
|
end else if ($past(pre_sign))
|
|
begin
|
|
if ($past(r_dividend[BW-1]))
|
|
assert(r_dividend == -$past(r_dividend));
|
|
if ($past(r_divisor[(2*BW-2)]))
|
|
begin
|
|
assert(r_divisor[(2*BW-2):(BW-1)]
|
|
== -$past(r_divisor[(2*BW-2):(BW-1)]));
|
|
assert(r_divisor[BW-2:0] == 0);
|
|
end
|
|
end else begin
|
|
if (o_quotient[0])
|
|
begin
|
|
assert(r_dividend == $past(diff));
|
|
end else
|
|
assert(r_dividend == $past(r_dividend));
|
|
|
|
// r_divisor should shift down on every step
|
|
assert(r_divisor[2*BW-2]==0);
|
|
assert(r_divisor[2*BW-3:0]==$past(r_divisor[2*BW-2:1]));
|
|
end
|
|
if ($past(r_dividend) >= $past(r_divisor[BW-1:0]))
|
|
begin
|
|
assert(o_quotient[0]);
|
|
end else
|
|
assert(!o_quotient[0]);
|
|
end
|
|
*/
|
|
|
|
always @(*)
|
|
if (r_busy)
|
|
assert((f_bits_set & r_dividend[BW-1:0])==0);
|
|
|
|
always @(*)
|
|
if (r_busy)
|
|
assert((r_divisor == 0) == zero_divisor);
|
|
|
|
`ifdef VERIFIC
|
|
// {{{
|
|
// Verify unsigned division
|
|
assert property (@(posedge i_clk)
|
|
disable iff (i_reset)
|
|
(i_wr)&&(i_denominator != 0)&&(!i_signed)
|
|
|=> ((!o_err)&&(!o_valid)&&(o_busy)&&(!r_sign)&&(!pre_sign)
|
|
throughout (r_bit == 0)
|
|
##1 ((r_bit == $past(r_bit)+1)&&({1'b0,r_bit}< BW-1))
|
|
[*0:$]
|
|
##1 ({ 1'b0, r_bit } == BW-1))
|
|
##1 (!o_err)&&(o_valid));
|
|
|
|
// Verify division by zero
|
|
assert property (@(posedge i_clk)
|
|
disable iff (i_reset)
|
|
(i_wr)&&(i_denominator == 0)
|
|
|=> (zero_divisor throughout
|
|
(!o_err)&&(!o_valid)&&(pre_sign) [*0:1]
|
|
##1 ((r_busy)&&(!o_err)&&(!o_valid))
|
|
##1 ((o_err)&&(o_valid))));
|
|
|
|
// }}}
|
|
`endif // VERIFIC
|
|
`endif
|
|
// }}}
|
|
endmodule
|
|
//
|
|
// How much logic will this divide use, now that it's been updated to
|
|
// a different (long division) algorithm?
|
|
//
|
|
// iCE40 stats (Updated) (Original)
|
|
// Number of cells: 700 820
|
|
// SB_CARRY 125 125
|
|
// SB_DFF 1
|
|
// SB_DFFE 33 1
|
|
// SB_DFFESR 37
|
|
// SB_DFFESS 31
|
|
// SB_DFFSR 40 40
|
|
// SB_LUT4 433 553
|
|
//
|
|
// Xilinx stats (Updated) (Original)
|
|
// Number of cells: 758 831
|
|
// FDRE 142 142
|
|
// LUT1 97 97
|
|
// LUT2 69 174
|
|
// LUT3 6 5
|
|
// LUT4 1 6
|
|
// LUT5 68 35
|
|
// LUT6 94 98
|
|
// MUXCY 129 129
|
|
// MUXF7 12 8
|
|
// MUXF8 6 3
|
|
// XORCY 134 134
|
|
|