41 lines
1.5 KiB
Verilog
41 lines
1.5 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: builddate.v
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// {{{
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// Project: 10Gb Ethernet switch
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//
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// Purpose: This file records the date of the last build. Running "make"
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// in the main directory will create this file. The `define found
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// within it then creates a version stamp that can be used to tell which
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// configuration is within an FPGA and so forth.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2023, Gisselquist Technology, LLC
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// {{{
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// This file is part of the ETH10G project.
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//
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// The ETH10G project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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// }}}
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// http://www.apache.org/licenses/LICENSE-2.0
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// {{{
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// Unless required by applicable law or agreed to in writing, files
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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`ifndef DATESTAMP
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`define DATESTAMP 32'h20230723
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`define BUILDTIME 32'h00082055
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`endif
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//
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