65 lines
1.8 KiB
Plaintext
65 lines
1.8 KiB
Plaintext
[tasks]
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prf2lanes_83MHz prf opt_2lanes opt_83MHz opt_with_ODELAY
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prf4lanes_83MHz prf opt_4lanes opt_83MHz opt_with_ODELAY
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prf8lanes_83MHz prf opt_8lanes opt_83MHz opt_with_ODELAY opt_WB_ERR
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prf2lanes_100MHz prf opt_2lanes opt_100MHz opt_with_ODELAY opt_WB_ERR
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prf4lanes_100MHz prf opt_4lanes opt_100MHz opt_with_ODELAY
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prf8lanes_100MHz prf opt_8lanes opt_100MHz opt_with_ODELAY
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prf_no_ODELAY prf opt_8lanes opt_100MHz
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[options]
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prf: mode prove
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prf: depth 7
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[engines]
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prf: smtbmc
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[script]
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read -formal ddr3_controller.v
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read -formal fwb_slave.v
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--pycode-begin--
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# Number of Lanes
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if "opt_2lanes" in tags:
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cmd = "chparam -set LANES 2 ddr3_controller\n"
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elif "opt_4lanes" in tags:
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cmd = "chparam -set LANES 4 ddr3_controller\n"
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elif "opt_8lanes" in tags:
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cmd = "chparam -set LANES 8 ddr3_controller\n"
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else:
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cmd = "chparam -set LANES 8 ddr3_controller\n"
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# Clock period
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if "opt_83MHz" in tags:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 12000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 3000 ddr3_controller\n"
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elif "opt_100MHz" in tags:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"
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else:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"
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# ODELAY support
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if "opt_with_ODELAY" in tags:
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cmd += "chparam -set ODELAY_SUPPORTED 1 ddr3_controller\n"
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else:
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cmd += "chparam -set ODELAY_SUPPORTED 0 ddr3_controller\n"
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# Wishbone Error
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if "opt_WB_ERR" in tags:
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cmd += "chparam -set WB_ERROR 1 ddr3_controller\n"
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else:
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cmd += "chparam -set WB_ERROR 0 ddr3_controller\n"
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output(cmd)
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--pycode-end--
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prep -top ddr3_controller
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[files]
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./rtl/ddr3_controller.v
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./formal/fwb_slave.v
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