37 lines
1.7 KiB
Tcl
37 lines
1.7 KiB
Tcl
############## clock define##################
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create_clock -period 5.000 [get_ports sys_clk_p]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
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# no need to create_clock for N side (only P side) or else tool will analyze interclock oaths and show failure in timing
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# https://support.xilinx.com/s/article/57109?language=en_US
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#create_clock -period 5.000 [get_ports sys_clk_n]
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set_property PACKAGE_PIN AE10 [get_ports sys_clk_p]
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set_property PACKAGE_PIN AF10 [get_ports sys_clk_n]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
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############## SODIMM SPD define##################
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set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl]
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set_property PACKAGE_PIN B20 [get_ports i2c_scl]
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set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda]
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set_property PACKAGE_PIN C20 [get_ports i2c_sda]
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############## fan define##################
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set_property IOSTANDARD LVCMOS25 [get_ports fan_pwm]
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set_property PACKAGE_PIN AE26 [get_ports fan_pwm]
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############## key define##################
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set_property PACKAGE_PIN AG27 [get_ports i_rst_n]
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set_property IOSTANDARD LVCMOS25 [get_ports i_rst_n]
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##############LED define##################
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set_property PACKAGE_PIN A22 [get_ports {led[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
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set_property PACKAGE_PIN C19 [get_ports {led[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
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set_property PACKAGE_PIN B19 [get_ports {led[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
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set_property PACKAGE_PIN E18 [get_ports {led[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
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##############uart define###########################
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set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
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set_property PACKAGE_PIN AK26 [get_ports uart_tx] |