3380 lines
266 KiB
C++
3380 lines
266 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Design internal header
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// See Vmain.h for the primary calling header
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#ifndef VERILATED_VMAIN___024ROOT_H_
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#define VERILATED_VMAIN___024ROOT_H_ // guard
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#include "verilated.h"
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class Vmain__Syms;
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class alignas(VL_CACHE_LINE_BYTES) Vmain___024root final : public VerilatedModule {
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public:
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// DESIGN SPECIFIC STATE
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// Anonymous structures to workaround compiler member-count bugs
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struct {
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VL_IN8(i_clk,0,0);
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CData/*0:0*/ main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n;
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VL_IN8(i_reset,0,0);
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VL_IN8(i_ddr3_controller_idelayctrl_rdy,0,0);
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VL_OUT8(o_ddr3_controller_dqs_tri_control,0,0);
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VL_OUT8(o_ddr3_controller_dq_tri_control,0,0);
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VL_OUT8(o_ddr3_controller_toggle_dqs,0,0);
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VL_OUT8(o_ddr3_controller_odelay_data_cntvaluein,4,0);
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VL_OUT8(o_ddr3_controller_odelay_dqs_cntvaluein,4,0);
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VL_OUT8(o_ddr3_controller_idelay_data_cntvaluein,4,0);
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VL_OUT8(o_ddr3_controller_idelay_dqs_cntvaluein,4,0);
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VL_OUT8(o_ddr3_controller_odelay_data_ld,7,0);
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VL_OUT8(o_ddr3_controller_odelay_dqs_ld,7,0);
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VL_OUT8(o_ddr3_controller_idelay_data_ld,7,0);
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VL_OUT8(o_ddr3_controller_idelay_dqs_ld,7,0);
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VL_OUT8(o_ddr3_controller_bitslip,7,0);
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VL_OUT8(o_sirefclk_word,7,0);
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VL_OUT8(o_sirefclk_ce,0,0);
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VL_IN8(i_fan_sda,0,0);
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VL_IN8(i_fan_scl,0,0);
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VL_OUT8(o_fan_sda,0,0);
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VL_OUT8(o_fan_scl,0,0);
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VL_OUT8(o_fpga_pwm,0,0);
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VL_OUT8(o_sys_pwm,0,0);
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VL_IN8(i_fan_tach,0,0);
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VL_OUT8(o_emmc_clk,0,0);
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VL_IN8(i_emmc_ds,0,0);
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VL_OUT8(io_emmc_cmd_tristate,0,0);
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VL_OUT8(o_emmc_cmd,0,0);
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VL_IN8(i_emmc_cmd,0,0);
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VL_OUT8(io_emmc_dat_tristate,7,0);
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VL_OUT8(o_emmc_dat,7,0);
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VL_IN8(i_emmc_dat,7,0);
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VL_IN8(i_emmc_detect,0,0);
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VL_IN8(i_i2c_sda,0,0);
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VL_IN8(i_i2c_scl,0,0);
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VL_OUT8(o_i2c_sda,0,0);
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VL_OUT8(o_i2c_scl,0,0);
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VL_OUT8(o_sdcard_clk,0,0);
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VL_IN8(i_sdcard_ds,0,0);
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VL_OUT8(io_sdcard_cmd_tristate,0,0);
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VL_OUT8(o_sdcard_cmd,0,0);
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VL_IN8(i_sdcard_cmd,0,0);
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VL_OUT8(io_sdcard_dat_tristate,3,0);
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VL_OUT8(o_sdcard_dat,3,0);
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VL_IN8(i_sdcard_dat,3,0);
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VL_IN8(i_sdcard_detect,0,0);
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VL_IN8(cpu_sim_cyc,0,0);
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VL_IN8(cpu_sim_stb,0,0);
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VL_IN8(cpu_sim_we,0,0);
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VL_IN8(cpu_sim_addr,6,0);
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VL_OUT8(cpu_sim_stall,0,0);
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VL_OUT8(cpu_sim_ack,0,0);
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VL_OUT8(cpu_prof_stb,0,0);
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VL_IN8(i_cpu_reset,0,0);
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VL_IN8(i_clk200,0,0);
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VL_IN8(i_wbu_uart_rx,0,0);
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VL_OUT8(o_wbu_uart_tx,0,0);
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VL_OUT8(o_wbu_uart_cts_n,0,0);
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VL_OUT8(o_gpio,7,0);
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VL_IN8(i_sw,7,0);
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VL_IN8(i_btn,4,0);
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VL_OUT8(o_led,7,0);
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CData/*0:0*/ main__DOT__emmcscope_int;
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};
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struct {
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CData/*0:0*/ main__DOT__sdioscope_int;
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CData/*0:0*/ main__DOT__emmc_int;
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CData/*0:0*/ main__DOT__sdcard_int;
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CData/*0:0*/ main__DOT__i2cscope_int;
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CData/*0:0*/ main__DOT__gpio_int;
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CData/*0:0*/ main__DOT__spio_int;
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CData/*0:0*/ main__DOT__r_sirefclk_en;
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CData/*0:0*/ main__DOT__w_sirefclk_unused_stb;
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CData/*0:0*/ main__DOT__r_sirefclk_ack;
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CData/*0:0*/ main__DOT__i2cdma_ready;
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CData/*0:0*/ main__DOT__i2c_valid;
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CData/*0:0*/ main__DOT__i2c_ready;
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CData/*0:0*/ main__DOT__i2c_last;
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CData/*7:0*/ main__DOT__i2c_data;
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CData/*0:0*/ main__DOT__w_console_rx_stb;
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CData/*0:0*/ main__DOT__w_console_busy;
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CData/*6:0*/ main__DOT__w_console_rx_data;
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CData/*6:0*/ main__DOT__w_console_tx_data;
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CData/*0:0*/ main__DOT__raw_cpu_dbg_stall;
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CData/*0:0*/ main__DOT__raw_cpu_dbg_ack;
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CData/*0:0*/ main__DOT__zip_cpu_int;
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CData/*7:0*/ main__DOT__wbu_rx_data;
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CData/*0:0*/ main__DOT__wbu_rx_stb;
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CData/*7:0*/ main__DOT__w_led;
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CData/*0:0*/ main__DOT__wbwide_i2cdma_cyc;
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CData/*0:0*/ main__DOT__wbwide_i2cdma_stb;
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CData/*0:0*/ main__DOT__wbwide_i2cm_cyc;
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CData/*0:0*/ main__DOT__wbwide_i2cm_stb;
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CData/*0:0*/ main__DOT__wbwide_zip_cyc;
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CData/*0:0*/ main__DOT__wbwide_zip_stb;
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CData/*0:0*/ main__DOT__wbwide_wbu_arbiter_cyc;
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CData/*0:0*/ main__DOT__wbwide_wbu_arbiter_stb;
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CData/*0:0*/ main__DOT__wbwide_wbdown_stall;
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CData/*0:0*/ main__DOT__wbwide_bkram_ack;
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CData/*0:0*/ main__DOT__wbwide_ddr3_controller_stall;
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CData/*0:0*/ main__DOT__wb32_wbdown_cyc;
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CData/*0:0*/ main__DOT__wb32_wbdown_stb;
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CData/*0:0*/ main__DOT__wb32_wbdown_err;
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CData/*7:0*/ main__DOT__wb32_buildtime_addr;
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CData/*0:0*/ main__DOT__wb32_buildtime_err;
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CData/*7:0*/ main__DOT__wb32_gpio_addr;
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CData/*0:0*/ main__DOT__wb32_gpio_err;
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CData/*0:0*/ main__DOT__wb32_sirefclk_stb;
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CData/*7:0*/ main__DOT__wb32_sirefclk_addr;
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CData/*0:0*/ main__DOT__wb32_sirefclk_err;
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CData/*0:0*/ main__DOT__wb32_spio_stb;
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CData/*7:0*/ main__DOT__wb32_spio_addr;
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CData/*0:0*/ main__DOT__wb32_spio_ack;
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CData/*0:0*/ main__DOT__wb32_spio_err;
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CData/*7:0*/ main__DOT__wb32_version_addr;
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CData/*0:0*/ main__DOT__wb32_version_err;
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CData/*0:0*/ main__DOT__wb32_i2cs_ack;
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CData/*0:0*/ main__DOT__wb32_i2cdma_ack;
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CData/*0:0*/ main__DOT__wb32_uart_ack;
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CData/*0:0*/ main__DOT__wb32_emmc_ack;
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CData/*0:0*/ main__DOT__wb32_fan_ack;
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CData/*0:0*/ main__DOT__wb32_sdcard_ack;
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CData/*0:0*/ main__DOT__wb32_ddr3_phy_stall;
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CData/*0:0*/ main__DOT__wb32_ddr3_phy_ack;
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CData/*0:0*/ main__DOT__wbu_cyc;
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CData/*0:0*/ main__DOT__wbu_stb;
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CData/*0:0*/ main__DOT__wbu_we;
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CData/*0:0*/ main__DOT__wbu_err;
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CData/*0:0*/ main__DOT__wbu_wbu_arbiter_stall;
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};
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struct {
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CData/*2:0*/ main__DOT____Vcellout__wbwide_xbar__o_swe;
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CData/*2:0*/ main__DOT____Vcellout__wbwide_xbar__o_sstb;
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CData/*2:0*/ main__DOT____Vcellout__wbwide_xbar__o_scyc;
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CData/*3:0*/ main__DOT____Vcellout__wbwide_xbar__o_merr;
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CData/*3:0*/ main__DOT____Vcellinp__wbwide_xbar__i_mcyc;
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CData/*0:0*/ main__DOT__r_wb32_sio_ack;
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CData/*7:0*/ main__DOT____Vcellout__wbu_xbar__o_ssel;
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CData/*1:0*/ main__DOT____Vcellout__wbu_xbar__o_swe;
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CData/*1:0*/ main__DOT____Vcellout__wbu_xbar__o_sstb;
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CData/*1:0*/ main__DOT____Vcellout__wbu_xbar__o_scyc;
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CData/*0:0*/ main__DOT____Vcellinp__emmcscopei____pinNumber3;
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CData/*0:0*/ main__DOT____Vcellinp__sdioscopei____pinNumber3;
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CData/*0:0*/ main__DOT____Vcellinp__u_i2cdma__S_VALID;
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CData/*6:0*/ main__DOT____Vcellinp__swic__i_dbg_addr;
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CData/*0:0*/ main__DOT____Vcellinp__swic__i_dbg_we;
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CData/*0:0*/ main__DOT____Vcellinp__swic__i_dbg_stb;
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CData/*0:0*/ main__DOT____Vcellinp__swic__i_dbg_cyc;
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CData/*0:0*/ main__DOT____Vcellinp__swic__i_reset;
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CData/*0:0*/ main__DOT__r_cfg_ack;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mgrant;
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CData/*2:0*/ main__DOT__wbwide_xbar__DOT__sgrant;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mfull;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mnearfull;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mempty;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__m_stb;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__m_we;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__m_stall;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__s_stall;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__s_ack;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__s_err;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__decoded;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskd_ready;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__decoded;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskd_ready;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__decoded;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskd_ready;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant;
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};
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struct {
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel;
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CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex;
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CData/*3:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant;
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CData/*1:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex;
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|
CData/*1:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex;
|
|
CData/*3:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant;
|
|
CData/*1:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex;
|
|
CData/*1:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex;
|
|
CData/*3:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant;
|
|
CData/*1:0*/ main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex;
|
|
CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack;
|
|
CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr;
|
|
CData/*5:0*/ main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending;
|
|
CData/*5:0*/ main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending;
|
|
CData/*5:0*/ main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending;
|
|
CData/*5:0*/ main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest;
|
|
CData/*2:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS;
|
|
CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__mgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__mfull;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__mnearfull;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__mempty;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__m_stb;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__m_stall;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__dcd_stb;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset;
|
|
CData/*7:0*/ main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available;
|
|
CData/*3:0*/ main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex;
|
|
CData/*3:0*/ main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr;
|
|
CData/*5:0*/ main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS;
|
|
CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__mgrant;
|
|
CData/*1:0*/ main__DOT__wbu_xbar__DOT__sgrant;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__mfull;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__mnearfull;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__mempty;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__m_stb;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__m_stall;
|
|
CData/*3:0*/ main__DOT__wbu_xbar__DOT__s_stall;
|
|
CData/*3:0*/ main__DOT__wbu_xbar__DOT__s_err;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__dcd_stb;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall;
|
|
CData/*2:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available;
|
|
CData/*1:0*/ main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex;
|
|
CData/*2:0*/ main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant;
|
|
CData/*1:0*/ main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr;
|
|
CData/*5:0*/ main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid;
|
|
CData/*1:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS;
|
|
CData/*0:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__read_from_data;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__write_to_control;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__read_address;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__bw_reset_request;
|
|
CData/*2:0*/ main__DOT__emmcscopei__DOT__br_config;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__dr_triggered;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__dr_primed;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__dw_trigger;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__dr_stopped;
|
|
CData/*4:0*/ main__DOT__emmcscopei__DOT__dr_stop_pipe;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__dr_force_write;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__dr_run_timeout;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__new_data;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__dr_force_inhibit;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__imm_adr;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__lst_adr;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__record_ce;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__br_wb_ack;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__br_pre_wb_ack;
|
|
CData/*0:0*/ main__DOT__emmcscopei__DOT__br_level_interrupt;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__read_from_data;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__write_to_control;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__read_address;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__bw_reset_request;
|
|
CData/*2:0*/ main__DOT__sdioscopei__DOT__br_config;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__dr_triggered;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__dr_primed;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__dw_trigger;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__dr_stopped;
|
|
CData/*4:0*/ main__DOT__sdioscopei__DOT__dr_stop_pipe;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__dr_force_write;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__dr_run_timeout;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__new_data;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__dr_force_inhibit;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__imm_adr;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__lst_adr;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__record_ce;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__br_wb_ack;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__br_pre_wb_ack;
|
|
CData/*0:0*/ main__DOT__sdioscopei__DOT__br_level_interrupt;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__instruction_address;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__reset_done;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__pause_counter;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_update;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_stall;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_stall;
|
|
CData/*7:0*/ main__DOT__ddr3_controller_inst__DOT__bank_status_q;
|
|
CData/*7:0*/ main__DOT__ddr3_controller_inst__DOT__bank_status_d;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_pending;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_aux;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_we;
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_bank;
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_next_bank;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_pending;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_aux;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_we;
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_bank;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__cmd_odt_q;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__cmd_odt;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__cmd_ck_en;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__cmd_reset_n;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__activate_slot_busy;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__write_dqs_q;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_dqs_d;
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__write_dqs;
|
|
};
|
|
struct {
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__write_dqs_val;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_dq_q;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_dq_d;
|
|
CData/*3:0*/ main__DOT__ddr3_controller_inst__DOT__write_dq;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__serial_index;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__serial_index_q;
|
|
CData/*7:0*/ main__DOT__ddr3_controller_inst__DOT__test_OFB;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__state_calibrate;
|
|
CData/*3:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat;
|
|
CData/*5:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_start_index;
|
|
CData/*5:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored;
|
|
CData/*5:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_target_index;
|
|
CData/*5:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig;
|
|
CData/*5:0*/ main__DOT__ddr3_controller_inst__DOT__dq_target_index;
|
|
CData/*5:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__train_delay;
|
|
CData/*3:0*/ main__DOT__ddr3_controller_inst__DOT__delay_before_read_data;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__initial_dqs;
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__lane;
|
|
CData/*5:0*/ main__DOT__ddr3_controller_inst__DOT__lane_times_8;
|
|
CData/*3:0*/ main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__index_read_pipe;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__index_wb_data;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_stb;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_aux;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_we;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_odt;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_dqs;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_dq;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_stb;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_update;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_we;
|
|
CData/*3:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_sel;
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_read_lane;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_cntvaluein;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_cntvaluein;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_cntvaluein;
|
|
CData/*4:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_cntvaluein;
|
|
CData/*7:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_ld;
|
|
CData/*7:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_ld;
|
|
CData/*7:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_ld;
|
|
CData/*7:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_ld;
|
|
CData/*2:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_write_lane;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__slot_number;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__read_slot;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__write_slot;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__anticipate_activate_slot;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__anticipate_precharge_slot;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT____Vlvbound_h133f9401__0;
|
|
CData/*0:0*/ main__DOT__ddr3_controller_inst__DOT____Vlvbound_hddcbe2f8__0;
|
|
CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1;
|
|
CData/*0:0*/ main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_wstb;
|
|
CData/*0:0*/ main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_stb;
|
|
CData/*5:0*/ main__DOT__u_i2cdma__DOT__subaddr;
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__wb_last;
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__bus_err;
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__r_reset;
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__r_overflow;
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__skd_valid;
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__skd_ready;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid;
|
|
CData/*0:0*/ main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__ck_tach;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__last_tach;
|
|
CData/*1:0*/ main__DOT__u_fan__DOT__pipe_tach;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__tach_reset;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__i2c_wb_ack;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__ign_mem_cyc;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__mem_stb;
|
|
CData/*4:0*/ main__DOT__u_fan__DOT__mem_addr;
|
|
CData/*7:0*/ main__DOT__u_fan__DOT__mem_data;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__mem_ack;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__i2cd_valid;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__i2cd_last;
|
|
CData/*7:0*/ main__DOT__u_fan__DOT__i2cd_data;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__pp_ms;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__pre_ack;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc;
|
|
CData/*4:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready;
|
|
CData/*7:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn;
|
|
CData/*4:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid;
|
|
CData/*7:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid;
|
|
CData/*3:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch;
|
|
CData/*4:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__abort_address;
|
|
CData/*4:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__jump_target;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__last_stb;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle;
|
|
CData/*7:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_word;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid;
|
|
CData/*1:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack;
|
|
CData/*3:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state;
|
|
CData/*2:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits;
|
|
CData/*7:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_scl;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_sda;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_scl;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_sda;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__stop_bit;
|
|
CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__cfg_ddr;
|
|
CData/*4:0*/ main__DOT__u_emmc__DOT__cfg_sample_shift;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__sdclk;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__pp_cmd;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__pp_data;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__rx_en;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__clk_ckspd;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb;
|
|
CData/*5:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb;
|
|
CData/*6:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode;
|
|
CData/*3:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_ack;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel;
|
|
CData/*3:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a;
|
|
};
|
|
struct {
|
|
CData/*3:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active;
|
|
CData/*5:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout;
|
|
CData/*6:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready;
|
|
CData/*3:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid;
|
|
CData/*4:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit;
|
|
CData/*4:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb;
|
|
CData/*3:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb;
|
|
CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg;
|
|
CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck;
|
|
CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__cpu_new_pc;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__pf_valid;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__pf_ready;
|
|
CData/*7:0*/ main__DOT__i2ci__DOT__pf_insn;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__pf_illegal;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__half_valid;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__imm_cycle;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__next_valid;
|
|
CData/*7:0*/ main__DOT__i2ci__DOT__next_insn;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__insn_ready;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__half_ready;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__i2c_abort;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__insn_valid;
|
|
CData/*3:0*/ main__DOT__i2ci__DOT__half_insn;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__i2c_ckedge;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__i2c_stretch;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__r_wait;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__soft_halt_request;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__r_halted;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__r_err;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__r_aborted;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__w_sda;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__w_scl;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__bus_write;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__bus_override;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__bus_manual;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__ovw_ready;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__bus_jump;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__s_tvalid;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt;
|
|
CData/*1:0*/ main__DOT__i2ci__DOT__GEN_TID__DOT__r_channel;
|
|
CData/*1:0*/ main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__last_stb;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid;
|
|
CData/*1:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__inflight;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__r_valid;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid;
|
|
CData/*6:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count;
|
|
CData/*5:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__dir;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack;
|
|
CData/*3:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__state;
|
|
};
|
|
struct {
|
|
CData/*2:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits;
|
|
CData/*7:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit;
|
|
CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first;
|
|
CData/*7:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last;
|
|
CData/*3:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift;
|
|
CData/*3:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty;
|
|
CData/*5:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill;
|
|
CData/*4:0*/ main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data;
|
|
CData/*4:0*/ main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty;
|
|
CData/*5:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr;
|
|
CData/*5:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr;
|
|
CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__cfg_ddr;
|
|
CData/*4:0*/ main__DOT__u_sdcard__DOT__cfg_sample_shift;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__sdclk;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__pp_cmd;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__pp_data;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__rx_en;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb;
|
|
CData/*5:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb;
|
|
CData/*6:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode;
|
|
CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_ack;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel;
|
|
CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a;
|
|
CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request;
|
|
CData/*2:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__clk90;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active;
|
|
CData/*5:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout;
|
|
CData/*6:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready;
|
|
CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid;
|
|
CData/*4:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit;
|
|
CData/*4:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid;
|
|
};
|
|
struct {
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb;
|
|
CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge;
|
|
CData/*5:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg;
|
|
CData/*5:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__io_started;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin;
|
|
CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__high_z;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n;
|
|
};
|
|
struct {
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p;
|
|
CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n;
|
|
CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in;
|
|
CData/*0:0*/ main__DOT__console__DOT__rx_uart_reset;
|
|
CData/*6:0*/ main__DOT__console__DOT__rxf_wb_data;
|
|
CData/*0:0*/ main__DOT__console__DOT__rxf_wb_read;
|
|
CData/*0:0*/ main__DOT__console__DOT__txf_wb_write;
|
|
CData/*0:0*/ main__DOT__console__DOT__tx_uart_reset;
|
|
CData/*6:0*/ main__DOT__console__DOT__txf_wb_data;
|
|
CData/*1:0*/ main__DOT__console__DOT__r_wb_addr;
|
|
CData/*0:0*/ main__DOT__console__DOT__r_wb_ack;
|
|
CData/*0:0*/ main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6;
|
|
CData/*0:0*/ main__DOT__console__DOT____VdfgTmp_h60af6732__0;
|
|
CData/*6:0*/ main__DOT__console__DOT__rxfifo__DOT__r_data;
|
|
CData/*6:0*/ main__DOT__console__DOT__rxfifo__DOT__last_write;
|
|
CData/*5:0*/ main__DOT__console__DOT__rxfifo__DOT__wr_addr;
|
|
CData/*5:0*/ main__DOT__console__DOT__rxfifo__DOT__rd_addr;
|
|
CData/*5:0*/ main__DOT__console__DOT__rxfifo__DOT__r_next;
|
|
CData/*0:0*/ main__DOT__console__DOT__rxfifo__DOT__will_overflow;
|
|
CData/*0:0*/ main__DOT__console__DOT__rxfifo__DOT__will_underflow;
|
|
CData/*0:0*/ main__DOT__console__DOT__rxfifo__DOT__osrc;
|
|
CData/*5:0*/ main__DOT__console__DOT__rxfifo__DOT__w_waddr_plus_one;
|
|
CData/*0:0*/ main__DOT__console__DOT__rxfifo__DOT__w_write;
|
|
CData/*0:0*/ main__DOT__console__DOT__rxfifo__DOT__w_read;
|
|
CData/*5:0*/ main__DOT__console__DOT__rxfifo__DOT__r_fill;
|
|
CData/*6:0*/ main__DOT__console__DOT__txfifo__DOT__r_data;
|
|
CData/*6:0*/ main__DOT__console__DOT__txfifo__DOT__last_write;
|
|
CData/*5:0*/ main__DOT__console__DOT__txfifo__DOT__wr_addr;
|
|
CData/*5:0*/ main__DOT__console__DOT__txfifo__DOT__rd_addr;
|
|
CData/*5:0*/ main__DOT__console__DOT__txfifo__DOT__r_next;
|
|
CData/*0:0*/ main__DOT__console__DOT__txfifo__DOT__will_overflow;
|
|
CData/*0:0*/ main__DOT__console__DOT__txfifo__DOT__will_underflow;
|
|
CData/*0:0*/ main__DOT__console__DOT__txfifo__DOT__osrc;
|
|
CData/*5:0*/ main__DOT__console__DOT__txfifo__DOT__w_waddr_plus_one;
|
|
CData/*0:0*/ main__DOT__console__DOT__txfifo__DOT__w_write;
|
|
CData/*0:0*/ main__DOT__console__DOT__txfifo__DOT__w_read;
|
|
CData/*5:0*/ main__DOT__console__DOT__txfifo__DOT__r_fill;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ctri_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__tma_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__tmb_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__tmc_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__jif_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dmac_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__mtc_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__moc_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__mpc_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__mic_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__utc_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__uoc_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__upc_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__uic_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__actr_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sys_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sys_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sys_we;
|
|
CData/*7:0*/ main__DOT__swic__DOT__sys_addr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sys_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sel_timer;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sel_pic;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sel_apic;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__swic__DOT__sel_watchdog;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sel_bus_watchdog;
|
|
CData/*0:0*/ main__DOT__swic__DOT__sel_dmac;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_we;
|
|
CData/*6:0*/ main__DOT__swic__DOT__dbg_addr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_stall;
|
|
CData/*3:0*/ main__DOT__swic__DOT__dbg_sel;
|
|
CData/*0:0*/ main__DOT__swic__DOT__no_dbg_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_break;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_cmd_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_cpu_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_cpu_read;
|
|
CData/*0:0*/ main__DOT__swic__DOT__reset_request;
|
|
CData/*0:0*/ main__DOT__swic__DOT__halt_request;
|
|
CData/*0:0*/ main__DOT__swic__DOT__step_request;
|
|
CData/*0:0*/ main__DOT__swic__DOT__clear_cache_request;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cmd_reset;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cmd_halt;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cmd_step;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cmd_clear_cache;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cmd_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cmd_read;
|
|
CData/*4:0*/ main__DOT__swic__DOT__cmd_waddr;
|
|
CData/*2:0*/ main__DOT__swic__DOT__cpu_dbg_cc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__wdt_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__wdt_reset;
|
|
CData/*0:0*/ main__DOT__swic__DOT__wdbus_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__wdbus_int;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_op_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_pf_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_i_count;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dmac_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dc_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dmac_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dc_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dc_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dc_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_gbl_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__tma_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__tmb_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__tmc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__jif_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_lcl_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_we;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__pic_interrupt;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cpu_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ext_err;
|
|
CData/*2:0*/ main__DOT__swic__DOT__w_ack_idx;
|
|
CData/*2:0*/ main__DOT__swic__DOT__ack_idx;
|
|
CData/*0:0*/ main__DOT__swic__DOT__last_sys_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__cmd_read_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__u_watchbus____pinNumber2;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__u_timer_a__i_wb_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__u_jiffies__i_wb_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__r_mmus_ack;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__swic__DOT__dbg_pre_ack;
|
|
CData/*1:0*/ main__DOT__swic__DOT__dbg_pre_addr;
|
|
CData/*4:0*/ main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter;
|
|
CData/*0:0*/ main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__r_reset_hold;
|
|
CData/*0:0*/ main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mtask_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mmstall_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mpstall_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mins_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__utask_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__umstall_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__upstall_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__uins_ctr____pinNumber5;
|
|
CData/*0:0*/ main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT____VdfgTmp_h145b7951__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_watchdog__DOT__r_running;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_watchdog__DOT__r_zero;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_watchdog__DOT__wb_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_a__DOT__r_running;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_a__DOT__r_zero;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_a__DOT__wb_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_b__DOT__r_running;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_b__DOT__r_zero;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_b__DOT__wb_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_c__DOT__r_running;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_c__DOT__r_zero;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_c__DOT__wb_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_jiffies__DOT__int_set;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_jiffies__DOT__new_set;
|
|
CData/*0:0*/ main__DOT__swic__DOT__u_jiffies__DOT__int_now;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_new_pc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_ready;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_illegal;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_ce;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_busy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_bus_err;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_wreg;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_we;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_ack;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubreak;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__step;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_u;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubus_err_flag;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_phase;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wR;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ALU;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_M;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_DIV;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_FP;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wF;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_break;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_lock;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_fpu;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_Rcc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF;
|
|
CData/*6:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_dbg_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags;
|
|
CData/*2:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__last_write_to_cc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset;
|
|
CData/*2:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc;
|
|
CData/*6:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R;
|
|
CData/*6:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A;
|
|
CData/*6:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset;
|
|
CData/*2:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc;
|
|
CData/*2:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc;
|
|
CData/*1:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Aid;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall;
|
|
CData/*1:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__regid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0;
|
|
};
|
|
struct {
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_lock;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_pc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_cc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op;
|
|
CData/*1:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid;
|
|
CData/*7:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h9ed30f6d__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_he52a0fcf__0;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__pre_sign;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0;
|
|
CData/*1:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe;
|
|
CData/*1:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_sgn;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_hi;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v;
|
|
CData/*7:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__rvsrc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last;
|
|
CData/*5:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc;
|
|
CData/*1:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__svmask;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort;
|
|
CData/*2:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__saddr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending;
|
|
CData/*7:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag;
|
|
CData/*1:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state;
|
|
CData/*5:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr;
|
|
CData/*5:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending;
|
|
CData/*2:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cline;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__in_cache;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie;
|
|
CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr;
|
|
CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__UNUSED_BITS__DOT__unused_aw;
|
|
CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner;
|
|
CData/*0:0*/ main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr;
|
|
CData/*3:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc;
|
|
CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size;
|
|
CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__rx_valid;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready;
|
|
CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_busy;
|
|
CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel;
|
|
CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size;
|
|
CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr;
|
|
CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr;
|
|
CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill;
|
|
CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes;
|
|
CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc;
|
|
CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size;
|
|
CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill;
|
|
CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes;
|
|
CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty;
|
|
CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr;
|
|
CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes;
|
|
CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc;
|
|
CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size;
|
|
CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner;
|
|
CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner;
|
|
CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie;
|
|
CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any;
|
|
CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints;
|
|
CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints;
|
|
CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie;
|
|
CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write;
|
|
CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints;
|
|
CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__read_from_data;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__write_to_control;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__read_address;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__bw_reset_request;
|
|
CData/*2:0*/ main__DOT__i2cscopei__DOT__br_config;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_triggered;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_primed;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__dw_trigger;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_stopped;
|
|
CData/*4:0*/ main__DOT__i2cscopei__DOT__dr_stop_pipe;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_force_write;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_run_timeout;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__new_data;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_force_inhibit;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__imm_adr;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__lst_adr;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__record_ce;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__br_wb_ack;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__br_pre_wb_ack;
|
|
CData/*0:0*/ main__DOT__i2cscopei__DOT__br_level_interrupt;
|
|
CData/*3:0*/ main__DOT__rcv__DOT__state;
|
|
CData/*6:0*/ main__DOT__rcv__DOT__baud_counter;
|
|
CData/*0:0*/ main__DOT__rcv__DOT__zero_baud_counter;
|
|
CData/*0:0*/ main__DOT__rcv__DOT__q_uart;
|
|
CData/*0:0*/ main__DOT__rcv__DOT__qq_uart;
|
|
CData/*0:0*/ main__DOT__rcv__DOT__ck_uart;
|
|
CData/*6:0*/ main__DOT__rcv__DOT__chg_counter;
|
|
CData/*0:0*/ main__DOT__rcv__DOT__half_baud_time;
|
|
CData/*7:0*/ main__DOT__rcv__DOT__data_reg;
|
|
CData/*6:0*/ main__DOT__txv__DOT__baud_counter;
|
|
CData/*3:0*/ main__DOT__txv__DOT__state;
|
|
CData/*7:0*/ main__DOT__txv__DOT__lcl_data;
|
|
CData/*0:0*/ main__DOT__txv__DOT__r_busy;
|
|
CData/*0:0*/ main__DOT__txv__DOT__zero_baud_counter;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__soft_reset;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__r_wdt_reset;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__rx_valid;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__in_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__ps_full;
|
|
CData/*7:0*/ main__DOT__genbus__DOT__ps_data;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wbu_tx_stb;
|
|
CData/*7:0*/ main__DOT__genbus__DOT__wbu_tx_data;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__exec_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__ofifo_rd;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__ofifo_empty_n;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__w_bus_busy;
|
|
CData/*0:0*/ main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__hx_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__hx_valid;
|
|
CData/*5:0*/ main__DOT__genbus__DOT__getinput__DOT__hx_hexbits;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__cw_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__cod_busy;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv;
|
|
CData/*2:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len;
|
|
CData/*2:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len;
|
|
CData/*1:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy;
|
|
CData/*7:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr;
|
|
};
|
|
struct {
|
|
CData/*7:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cmd_addr;
|
|
CData/*2:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb;
|
|
CData/*1:0*/ main__DOT__genbus__DOT__runwb__DOT__wb_state;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__r_inc;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__r_new_addr;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__last_read_request;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__last_ack;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__zero_acks;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__r_busy;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__dw_busy;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__cw_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__cp_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__dw_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__ln_stb;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__ln_busy;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__cp_busy;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__byte_busy;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__dw_bits;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__ln_bits;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__r_active;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy;
|
|
CData/*2:0*/ main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__newv;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid;
|
|
CData/*3:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch;
|
|
CData/*2:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_hlfd;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr;
|
|
CData/*6:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__nxt_wrptr;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write;
|
|
CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read;
|
|
CData/*0:0*/ main__DOT__spioi__DOT__led_demo;
|
|
CData/*7:0*/ main__DOT__spioi__DOT__r_led;
|
|
CData/*7:0*/ main__DOT__spioi__DOT__bounced;
|
|
CData/*0:0*/ main__DOT__spioi__DOT__sw_int;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__s_btn;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn;
|
|
CData/*0:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn_int;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int;
|
|
CData/*7:0*/ main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw;
|
|
CData/*7:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_owner;
|
|
CData/*0:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_dir;
|
|
CData/*0:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_clk;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__br_ctr;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness;
|
|
CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err;
|
|
CData/*3:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_shift;
|
|
CData/*5:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty;
|
|
CData/*5:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr;
|
|
CData/*5:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr;
|
|
CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd;
|
|
CData/*2:0*/ __VdfgTmp_h503d14d1__0;
|
|
CData/*1:0*/ __VdfgTmp_ha46ae6a3__0;
|
|
CData/*7:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data;
|
|
CData/*2:0*/ __Vdly__main__DOT__wbwide_xbar__DOT__sgrant;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v0;
|
|
CData/*3:0*/ __Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v2;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v3;
|
|
CData/*3:0*/ __Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v4;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v4;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v5;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v6;
|
|
CData/*3:0*/ __Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v7;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v7;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v8;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v9;
|
|
CData/*3:0*/ __Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v10;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v10;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v11;
|
|
CData/*2:0*/ __Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb;
|
|
CData/*5:0*/ __Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending;
|
|
CData/*3:0*/ __Vdly__main__DOT__wbwide_xbar__DOT__mnearfull;
|
|
CData/*5:0*/ __Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending;
|
|
CData/*5:0*/ __Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending;
|
|
CData/*5:0*/ __Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v2;
|
|
CData/*0:0*/ __Vdly__main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr;
|
|
CData/*5:0*/ __Vdly__main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending;
|
|
CData/*0:0*/ __Vdly__main__DOT__wb32_xbar__DOT__mnearfull;
|
|
CData/*1:0*/ __Vdly__main__DOT__wbu_xbar__DOT__sgrant;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v0;
|
|
CData/*2:0*/ __Vdlyvval__main__DOT__wbu_xbar__DOT__grant__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v1;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v2;
|
|
CData/*1:0*/ __Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb;
|
|
CData/*0:0*/ __Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr;
|
|
CData/*0:0*/ __Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack;
|
|
CData/*5:0*/ __Vdly__main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending;
|
|
CData/*0:0*/ __Vdly__main__DOT__wbu_xbar__DOT__mnearfull;
|
|
CData/*0:0*/ __Vdly__main__DOT__emmcscopei__DOT__dr_stopped;
|
|
CData/*4:0*/ __Vdly__main__DOT__emmcscopei__DOT__dr_stop_pipe;
|
|
CData/*0:0*/ __Vdly__main__DOT__emmcscopei__DOT__dr_force_inhibit;
|
|
CData/*0:0*/ __Vdly__main__DOT__emmcscopei__DOT__dr_force_write;
|
|
CData/*0:0*/ __Vdly__main__DOT__emmcscopei__DOT__dr_primed;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__emmcscopei__DOT__mem__v0;
|
|
CData/*0:0*/ __Vdly__main__DOT__sdioscopei__DOT__dr_stopped;
|
|
CData/*4:0*/ __Vdly__main__DOT__sdioscopei__DOT__dr_stop_pipe;
|
|
CData/*0:0*/ __Vdly__main__DOT__sdioscopei__DOT__dr_force_inhibit;
|
|
CData/*0:0*/ __Vdly__main__DOT__sdioscopei__DOT__dr_force_write;
|
|
CData/*0:0*/ __Vdly__main__DOT__sdioscopei__DOT__dr_primed;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__sdioscopei__DOT__mem__v0;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v0;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v1;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v2;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v2;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v3;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v3;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v4;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v4;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v5;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v5;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v6;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v6;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v7;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v7;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v8;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v8;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v9;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v9;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v10;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v10;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v11;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v11;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v12;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v12;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v13;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v13;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v14;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v14;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v15;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v15;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v16;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v16;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v17;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v17;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v18;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v18;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v19;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v19;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v20;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v20;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v21;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v21;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v22;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v22;
|
|
};
|
|
struct {
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v23;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v23;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v24;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v24;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v25;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v25;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v26;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v26;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v27;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v27;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v28;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v28;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v29;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v29;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v30;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v30;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v31;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v31;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v32;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v32;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v33;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v33;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v34;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v34;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v35;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v35;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v36;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v36;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v37;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v37;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v38;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v38;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v39;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v39;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v40;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v40;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v41;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v41;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v42;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v42;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v43;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v43;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v44;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v44;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v45;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v45;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v46;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v46;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v47;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v47;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v48;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v48;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v49;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v49;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v50;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v50;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v51;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v51;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v52;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v52;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v53;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v53;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v54;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v54;
|
|
};
|
|
struct {
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v55;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v55;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v56;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v56;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v57;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v57;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v58;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v58;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v59;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v59;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v60;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v60;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v61;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v61;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v62;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v62;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__bkrami__DOT__mem__v63;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__bkrami__DOT__mem__v63;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_i2cdma__DOT__bus_err;
|
|
CData/*0:0*/ __Vdly__main__DOT__wbwide_i2cdma_cyc;
|
|
CData/*5:0*/ __Vdly__main__DOT__u_i2cdma__DOT__subaddr;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_i2cdma__DOT__r_overflow;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__tach_reset;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle;
|
|
CData/*4:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__ign_mem_cyc;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__mem_stb;
|
|
CData/*1:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight;
|
|
CData/*4:0*/ __Vdly__main__DOT__u_fan__DOT__mem_addr;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid;
|
|
CData/*4:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda;
|
|
CData/*3:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state;
|
|
CData/*7:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg;
|
|
CData/*2:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__rx_en;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
};
|
|
struct {
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
CData/*5:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount;
|
|
CData/*7:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout;
|
|
CData/*6:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done;
|
|
CData/*1:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid;
|
|
CData/*3:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count;
|
|
CData/*4:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts;
|
|
CData/*4:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid;
|
|
CData/*1:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr;
|
|
CData/*1:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr;
|
|
CData/*3:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__imm_cycle;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__i2c_ckedge;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__r_halted;
|
|
CData/*0:0*/ __Vdly__main__DOT__wbwide_i2cm_cyc;
|
|
CData/*0:0*/ __Vdly__main__DOT__wbwide_i2cm_stb;
|
|
CData/*1:0*/ __Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__inflight;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid;
|
|
CData/*6:0*/ __Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__pf_valid;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__pf_illegal;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__w_sda;
|
|
CData/*3:0*/ __Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state;
|
|
CData/*7:0*/ __Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg;
|
|
CData/*2:0*/ __Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err;
|
|
CData/*5:0*/ __Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill;
|
|
CData/*5:0*/ __Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr;
|
|
CData/*4:0*/ __Vdlyvdim0__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0;
|
|
CData/*4:0*/ __Vdlyvval__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0;
|
|
CData/*5:0*/ __Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__rx_en;
|
|
CData/*2:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
};
|
|
struct {
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
CData/*5:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount;
|
|
CData/*7:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout;
|
|
CData/*6:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done;
|
|
CData/*1:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid;
|
|
CData/*3:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count;
|
|
CData/*4:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts;
|
|
CData/*4:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid;
|
|
CData/*1:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr;
|
|
CData/*1:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr;
|
|
CData/*3:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done;
|
|
CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy;
|
|
CData/*0:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__console__DOT__rxfifo__DOT__fifo__v0;
|
|
CData/*6:0*/ __Vdlyvval__main__DOT__console__DOT__rxfifo__DOT__fifo__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__console__DOT__rxfifo__DOT__fifo__v0;
|
|
CData/*0:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow;
|
|
CData/*5:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__rd_addr;
|
|
CData/*5:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill;
|
|
CData/*0:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__console__DOT__txfifo__DOT__fifo__v0;
|
|
CData/*6:0*/ __Vdlyvval__main__DOT__console__DOT__txfifo__DOT__fifo__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__console__DOT__txfifo__DOT__fifo__v0;
|
|
CData/*0:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow;
|
|
CData/*5:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__rd_addr;
|
|
CData/*5:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill;
|
|
CData/*4:0*/ __Vdly__main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_clear_cache;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_write;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_read;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_read_ack;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__wdt_reset;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__wdbus_int;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero;
|
|
CData/*1:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb;
|
|
CData/*2:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0;
|
|
CData/*5:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_illegal;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__dbg_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request;
|
|
CData/*1:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb;
|
|
CData/*6:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy;
|
|
CData/*6:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid;
|
|
CData/*5:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last;
|
|
CData/*4:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill;
|
|
CData/*4:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr;
|
|
CData/*3:0*/ __Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0;
|
|
CData/*4:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr;
|
|
CData/*6:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_stopped;
|
|
CData/*4:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_stop_pipe;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_force_inhibit;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_force_write;
|
|
CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_primed;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__i2cscopei__DOT__mem__v0;
|
|
CData/*6:0*/ __Vdly__main__DOT__rcv__DOT__chg_counter;
|
|
CData/*3:0*/ __Vdly__main__DOT__rcv__DOT__state;
|
|
CData/*7:0*/ __Vdly__main__DOT__rcv__DOT__data_reg;
|
|
CData/*6:0*/ __Vdly__main__DOT__rcv__DOT__baud_counter;
|
|
CData/*0:0*/ __Vdly__main__DOT__rcv__DOT__zero_baud_counter;
|
|
CData/*0:0*/ __Vdly__main__DOT__txv__DOT__r_busy;
|
|
CData/*7:0*/ __Vdly__main__DOT__txv__DOT__lcl_data;
|
|
CData/*0:0*/ __Vdly__main__DOT__txv__DOT__zero_baud_counter;
|
|
CData/*6:0*/ __Vdly__main__DOT__txv__DOT__baud_counter;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__r_wdt_reset;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__hx_stb;
|
|
CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len;
|
|
CData/*1:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw;
|
|
CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__cw_stb;
|
|
CData/*7:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr;
|
|
CData/*7:0*/ __Vdlyvdim0__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0;
|
|
CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb;
|
|
CData/*1:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state;
|
|
CData/*0:0*/ __Vdly__main__DOT__wbu_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__last_read_request;
|
|
CData/*6:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits;
|
|
CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len;
|
|
CData/*6:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wbu_tx_stb;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow;
|
|
CData/*6:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow;
|
|
CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__ofifo_empty_n;
|
|
CData/*7:0*/ __Vdly__o_gpio;
|
|
CData/*7:0*/ __Vdly__main__DOT__spioi__DOT__r_led;
|
|
CData/*7:0*/ __Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw;
|
|
CData/*7:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner;
|
|
CData/*0:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness;
|
|
CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness;
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CData/*0:0*/ __Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc;
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CData/*5:0*/ __Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill;
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CData/*5:0*/ __Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr;
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CData/*4:0*/ __Vdlyvdim0__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0;
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CData/*3:0*/ __Vdlyvval__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0;
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CData/*0:0*/ __Vdlyvset__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0;
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CData/*5:0*/ __Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr;
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CData/*2:0*/ __Vdly__main__DOT__emmcscopei__DOT__br_config;
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|
CData/*2:0*/ __Vdly__main__DOT__sdioscopei__DOT__br_config;
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|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe;
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|
CData/*1:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock;
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|
CData/*4:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp;
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CData/*1:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss;
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|
CData/*3:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0;
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|
CData/*4:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr;
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|
CData/*4:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr;
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CData/*7:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v;
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};
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struct {
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl;
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|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb;
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CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line;
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|
CData/*1:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state;
|
|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc;
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|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb;
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|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag;
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|
CData/*2:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0;
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|
CData/*5:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr;
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|
CData/*4:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending;
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|
CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0;
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|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1;
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|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2;
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|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2;
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CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3;
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|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4;
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|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9;
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|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12;
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|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12;
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CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13;
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CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14;
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|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16;
|
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CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16;
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|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17;
|
|
};
|
|
struct {
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38;
|
|
};
|
|
struct {
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59;
|
|
};
|
|
struct {
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62;
|
|
CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63;
|
|
CData/*7:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63;
|
|
CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63;
|
|
CData/*2:0*/ __Vdly__main__DOT__i2cscopei__DOT__br_config;
|
|
CData/*0:0*/ __Vtrigprevexpr___TOP__i_clk__0;
|
|
CData/*3:0*/ __Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0;
|
|
CData/*3:0*/ __Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0;
|
|
CData/*3:0*/ __Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0;
|
|
CData/*3:0*/ __Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0;
|
|
CData/*2:0*/ __Vtrigprevexpr___TOP__main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0;
|
|
CData/*0:0*/ __Vtrigprevexpr___TOP__main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n__0;
|
|
CData/*0:0*/ __VactDidInit;
|
|
CData/*0:0*/ __VactContinue;
|
|
VL_IN16(i_gpio,15,0);
|
|
SData/*11:0*/ main__DOT____Vcellout__wb32_xbar__o_swe;
|
|
SData/*11:0*/ main__DOT____Vcellout__wb32_xbar__o_sstb;
|
|
SData/*11:0*/ main__DOT____Vcellout__wb32_xbar__o_scyc;
|
|
SData/*11:0*/ main__DOT__wb32_xbar__DOT__sgrant;
|
|
SData/*15:0*/ main__DOT__wb32_xbar__DOT__s_stall;
|
|
SData/*12:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded;
|
|
SData/*12:0*/ main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant;
|
|
SData/*11:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest;
|
|
SData/*11:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request;
|
|
SData/*11:0*/ main__DOT__emmcscopei__DOT__raddr;
|
|
SData/*11:0*/ main__DOT__emmcscopei__DOT__waddr;
|
|
SData/*11:0*/ main__DOT__emmcscopei__DOT__this_addr;
|
|
SData/*11:0*/ main__DOT__sdioscopei__DOT__raddr;
|
|
SData/*11:0*/ main__DOT__sdioscopei__DOT__waddr;
|
|
SData/*11:0*/ main__DOT__sdioscopei__DOT__this_addr;
|
|
SData/*15:0*/ main__DOT__ddr3_controller_inst__DOT__delay_counter;
|
|
SData/*9:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_col;
|
|
SData/*13:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_row;
|
|
SData/*13:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_next_row;
|
|
SData/*9:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_col;
|
|
SData/*13:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_row;
|
|
SData/*15:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement;
|
|
SData/*9:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_col;
|
|
SData/*13:0*/ main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr;
|
|
SData/*8:0*/ main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data;
|
|
SData/*8:0*/ main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data;
|
|
SData/*8:0*/ main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_data;
|
|
SData/*12:0*/ main__DOT__u_fan__DOT__pwm_counter;
|
|
SData/*12:0*/ main__DOT__u_fan__DOT__ctl_fpga;
|
|
SData/*12:0*/ main__DOT__u_fan__DOT__ctl_sys;
|
|
SData/*11:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn;
|
|
SData/*11:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount;
|
|
SData/*11:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount;
|
|
SData/*9:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter;
|
|
};
|
|
struct {
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data;
|
|
SData/*9:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc;
|
|
SData/*11:0*/ main__DOT__i2ci__DOT__insn;
|
|
SData/*11:0*/ main__DOT__i2ci__DOT__i2c_ckcount;
|
|
SData/*11:0*/ main__DOT__i2ci__DOT__ckcount;
|
|
SData/*9:0*/ main__DOT__i2ci__DOT__ovw_data;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data;
|
|
SData/*9:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat;
|
|
SData/*15:0*/ main__DOT__console__DOT__rxf_status;
|
|
SData/*15:0*/ main__DOT__console__DOT__txf_status;
|
|
SData/*9:0*/ main__DOT__console__DOT__rxfifo__DOT__w_fill;
|
|
SData/*9:0*/ main__DOT__console__DOT__txfifo__DOT__w_fill;
|
|
SData/*14:0*/ main__DOT__swic__DOT__main_int_vector;
|
|
SData/*14:0*/ main__DOT__swic__DOT__alt_int_vector;
|
|
SData/*8:0*/ main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0;
|
|
SData/*13:0*/ main__DOT__swic__DOT__u_watchbus__DOT__r_value;
|
|
SData/*15:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags;
|
|
SData/*15:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags;
|
|
SData/*14:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_nxt_half;
|
|
SData/*12:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data;
|
|
SData/*11:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0;
|
|
SData/*10:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen;
|
|
SData/*10:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen;
|
|
SData/*10:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding;
|
|
SData/*10:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len;
|
|
SData/*10:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len;
|
|
SData/*9:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding;
|
|
SData/*14:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state;
|
|
SData/*14:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable;
|
|
SData/*14:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state;
|
|
SData/*14:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable;
|
|
SData/*9:0*/ main__DOT__i2cscopei__DOT__raddr;
|
|
SData/*9:0*/ main__DOT__i2cscopei__DOT__waddr;
|
|
};
|
|
struct {
|
|
SData/*9:0*/ main__DOT__i2cscopei__DOT__this_addr;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__rd_len;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__runwb__DOT__r_acks_needed;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__runwb__DOT__r_len;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__maddr;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld;
|
|
SData/*9:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr;
|
|
SData/*10:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr;
|
|
SData/*10:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr;
|
|
SData/*10:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__nxt_wrptr;
|
|
SData/*15:0*/ main__DOT__gpioi__DOT__r_gpio;
|
|
SData/*15:0*/ main__DOT__gpioi__DOT__x_gpio;
|
|
SData/*15:0*/ main__DOT__gpioi__DOT__q_gpio;
|
|
SData/*9:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe;
|
|
SData/*15:0*/ main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe;
|
|
SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout;
|
|
SData/*11:0*/ __Vdly__main__DOT__wb32_xbar__DOT__sgrant;
|
|
SData/*12:0*/ __Vdlyvval__main__DOT__wb32_xbar__DOT__grant__v1;
|
|
SData/*11:0*/ __Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb;
|
|
SData/*11:0*/ __Vdly__main__DOT__emmcscopei__DOT__waddr;
|
|
SData/*11:0*/ __Vdlyvdim0__main__DOT__emmcscopei__DOT__mem__v0;
|
|
SData/*11:0*/ __Vdly__main__DOT__sdioscopei__DOT__waddr;
|
|
SData/*11:0*/ __Vdlyvdim0__main__DOT__sdioscopei__DOT__mem__v0;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v0;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v0;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v1;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v1;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v2;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v2;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v3;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v3;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v4;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v4;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v5;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v5;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v6;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v6;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v7;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v7;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v8;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v8;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v9;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v9;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v10;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v10;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v11;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v11;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v12;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v12;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v13;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v13;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v14;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v14;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v15;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v15;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v16;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v16;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v17;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v17;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v18;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v18;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v19;
|
|
};
|
|
struct {
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v19;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v20;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v20;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v21;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v21;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v22;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v22;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v23;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v23;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v24;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v24;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v25;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v25;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v26;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v26;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v27;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v27;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v28;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v28;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v29;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v29;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v30;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v30;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v31;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v31;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v32;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v32;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v33;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v33;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v34;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v34;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v35;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v35;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v36;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v36;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v37;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v37;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v38;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v38;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v39;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v39;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v40;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v40;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v41;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v41;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v42;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v42;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v43;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v43;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v44;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v44;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v45;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v45;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v46;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v46;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v47;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v47;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v48;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v48;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v49;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v49;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v50;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v50;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v51;
|
|
};
|
|
struct {
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v51;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v52;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v52;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v53;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v53;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v54;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v54;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v55;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v55;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v56;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v56;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v57;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v57;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v58;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v58;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v59;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v59;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v60;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v60;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v61;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v61;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v62;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v62;
|
|
SData/*13:0*/ __Vdlyvdim0__main__DOT__bkrami__DOT__mem__v63;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__bkrami__DOT__mem__v63;
|
|
SData/*12:0*/ __Vdly__main__DOT__u_fan__DOT__ctl_sys;
|
|
SData/*12:0*/ __Vdly__main__DOT__u_fan__DOT__ctl_fpga;
|
|
SData/*12:0*/ __Vdly__main__DOT__u_fan__DOT__pwm_counter;
|
|
SData/*11:0*/ __Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc;
|
|
SData/*11:0*/ __Vdly__main__DOT__i2ci__DOT__i2c_ckcount;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2;
|
|
};
|
|
struct {
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg;
|
|
SData/*9:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc;
|
|
SData/*15:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc;
|
|
SData/*13:0*/ __Vdly__main__DOT__swic__DOT__u_watchbus__DOT__r_value;
|
|
SData/*15:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0;
|
|
SData/*10:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen;
|
|
SData/*10:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len;
|
|
SData/*10:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding;
|
|
SData/*10:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len;
|
|
SData/*9:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding;
|
|
SData/*14:0*/ __Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state;
|
|
SData/*14:0*/ __Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable;
|
|
SData/*14:0*/ __Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state;
|
|
SData/*14:0*/ __Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable;
|
|
SData/*9:0*/ __Vdly__main__DOT__i2cscopei__DOT__waddr;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__i2cscopei__DOT__mem__v0;
|
|
SData/*9:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__r_acks_needed;
|
|
SData/*9:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len;
|
|
SData/*9:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0;
|
|
SData/*9:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr;
|
|
SData/*9:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr;
|
|
SData/*9:0*/ __Vdlyvdim0__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0;
|
|
SData/*10:0*/ __Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr;
|
|
SData/*9:0*/ __Vdly__main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe;
|
|
SData/*15:0*/ __Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe;
|
|
SData/*11:0*/ __Vdly__main__DOT__emmcscopei__DOT__raddr;
|
|
SData/*11:0*/ __Vdly__main__DOT__sdioscopei__DOT__raddr;
|
|
SData/*11:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24;
|
|
};
|
|
struct {
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62;
|
|
SData/*8:0*/ __Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63;
|
|
SData/*9:0*/ __Vdly__main__DOT__i2cscopei__DOT__raddr;
|
|
SData/*12:0*/ __Vtrigprevexpr___TOP__main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0;
|
|
VL_INW(i_ddr3_controller_iserdes_data,511,0,16);
|
|
VL_OUTW(o_ddr3_controller_cmd,95,0,3);
|
|
VL_OUTW(o_ddr3_controller_data,511,0,16);
|
|
VL_IN(cpu_sim_data,31,0);
|
|
VL_OUT(cpu_sim_idata,31,0);
|
|
VL_OUT(cpu_prof_addr,27,0);
|
|
VL_OUT(cpu_prof_ticks,31,0);
|
|
IData/*29:0*/ main__DOT__r_sirefclk_data;
|
|
IData/*31:0*/ main__DOT__uart_debug;
|
|
IData/*21:0*/ main__DOT__wbwide_i2cdma_addr;
|
|
VlWide<16>/*511:0*/ main__DOT__wbwide_i2cdma_data;
|
|
IData/*21:0*/ main__DOT__wbwide_i2cm_addr;
|
|
IData/*21:0*/ main__DOT__wbwide_zip_addr;
|
|
VlWide<16>/*511:0*/ main__DOT__wbwide_bkram_idata;
|
|
IData/*31:0*/ main__DOT__wb32_wbdown_idata;
|
|
IData/*31:0*/ main__DOT__wb32_i2cdma_idata;
|
|
IData/*31:0*/ main__DOT__wb32_uart_idata;
|
|
IData/*31:0*/ main__DOT__wb32_emmc_idata;
|
|
IData/*31:0*/ main__DOT__wb32_fan_idata;
|
|
IData/*31:0*/ main__DOT__wb32_sdcard_idata;
|
|
IData/*31:0*/ main__DOT__wb32_ddr3_phy_idata;
|
|
IData/*31:0*/ main__DOT__wbu_data;
|
|
IData/*31:0*/ main__DOT__wbu_idata;
|
|
};
|
|
struct {
|
|
IData/*31:0*/ main__DOT__wbu_zip_idata;
|
|
VlWide<6>/*191:0*/ main__DOT____Vcellout__wbwide_xbar__o_ssel;
|
|
VlWide<48>/*1535:0*/ main__DOT____Vcellout__wbwide_xbar__o_sdata;
|
|
VlWide<3>/*65:0*/ main__DOT____Vcellout__wbwide_xbar__o_saddr;
|
|
VlWide<64>/*2047:0*/ main__DOT____Vcellout__wbwide_xbar__o_mdata;
|
|
IData/*31:0*/ main__DOT__r_wb32_sio_data;
|
|
VlWide<12>/*383:0*/ main__DOT____Vcellout__wb32_xbar__o_sdata;
|
|
VlWide<3>/*95:0*/ main__DOT____Vcellout__wb32_xbar__o_saddr;
|
|
IData/*30:0*/ main__DOT____Vcellinp__emmcscopei____pinNumber4;
|
|
IData/*30:0*/ main__DOT____Vcellinp__sdioscopei____pinNumber4;
|
|
IData/*31:0*/ main__DOT____Vcellinp__swic__i_dbg_data;
|
|
IData/*30:0*/ main__DOT____Vcellinp__i2cscopei____pinNumber4;
|
|
IData/*31:0*/ main__DOT__wbwide_xbar__DOT__iN;
|
|
IData/*31:0*/ main__DOT__wbwide_xbar__DOT__iM;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data;
|
|
VlWide<19>/*576:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data;
|
|
IData/*21:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data;
|
|
VlWide<19>/*576:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data;
|
|
IData/*21:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_addr;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data;
|
|
VlWide<19>/*576:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data;
|
|
IData/*21:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_addr;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data;
|
|
VlWide<19>/*576:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data;
|
|
IData/*21:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_addr;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data;
|
|
IData/*31:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data;
|
|
IData/*31:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__iM;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data;
|
|
IData/*31:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__iM;
|
|
VlWide<19>/*598:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data;
|
|
IData/*31:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__iM;
|
|
IData/*31:0*/ main__DOT__wb32_xbar__DOT__iN;
|
|
IData/*31:0*/ main__DOT__wb32_xbar__DOT__iM;
|
|
IData/*31:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM;
|
|
IData/*31:0*/ main__DOT__wbu_xbar__DOT__iN;
|
|
IData/*31:0*/ main__DOT__wbu_xbar__DOT__iM;
|
|
IData/*26:0*/ main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr;
|
|
IData/*31:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM;
|
|
IData/*31:0*/ main__DOT__emmcscopei__DOT__o_bus_data;
|
|
IData/*19:0*/ main__DOT__emmcscopei__DOT__br_holdoff;
|
|
IData/*19:0*/ main__DOT__emmcscopei__DOT__holdoff_counter;
|
|
IData/*30:0*/ main__DOT__emmcscopei__DOT__ck_addr;
|
|
IData/*30:0*/ main__DOT__emmcscopei__DOT__qd_data;
|
|
IData/*30:0*/ main__DOT__emmcscopei__DOT__lst_val;
|
|
IData/*30:0*/ main__DOT__emmcscopei__DOT__imm_val;
|
|
IData/*31:0*/ main__DOT__emmcscopei__DOT__r_data;
|
|
IData/*31:0*/ main__DOT__emmcscopei__DOT__nxt_mem;
|
|
IData/*31:0*/ main__DOT__sdioscopei__DOT__o_bus_data;
|
|
IData/*19:0*/ main__DOT__sdioscopei__DOT__br_holdoff;
|
|
IData/*19:0*/ main__DOT__sdioscopei__DOT__holdoff_counter;
|
|
IData/*30:0*/ main__DOT__sdioscopei__DOT__ck_addr;
|
|
IData/*30:0*/ main__DOT__sdioscopei__DOT__qd_data;
|
|
IData/*30:0*/ main__DOT__sdioscopei__DOT__lst_val;
|
|
IData/*30:0*/ main__DOT__sdioscopei__DOT__imm_val;
|
|
IData/*31:0*/ main__DOT__sdioscopei__DOT__r_data;
|
|
IData/*31:0*/ main__DOT__sdioscopei__DOT__nxt_mem;
|
|
IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__index;
|
|
IData/*27:0*/ main__DOT__ddr3_controller_inst__DOT__instruction;
|
|
};
|
|
struct {
|
|
VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_data;
|
|
VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned;
|
|
IData/*23:0*/ main__DOT__ddr3_controller_inst__DOT__aligned_cmd;
|
|
VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_data;
|
|
VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__read_data_store;
|
|
VlWide<4>/*127:0*/ main__DOT__ddr3_controller_inst__DOT__write_pattern;
|
|
IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_addr;
|
|
IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_data;
|
|
IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result;
|
|
IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__nCK_to_cycles__Vstatic__result;
|
|
IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__delay;
|
|
IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__find_delay__Vstatic__k;
|
|
VlWide<16>/*511:0*/ main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data;
|
|
IData/*31:0*/ main__DOT__bkrami__DOT__WRITE_TO_MEMORY__DOT__ik;
|
|
IData/*31:0*/ main__DOT__clock_generator__DOT__r_delay;
|
|
IData/*31:0*/ main__DOT__clock_generator__DOT__times_three;
|
|
IData/*31:0*/ main__DOT__clock_generator__DOT__times_five;
|
|
IData/*31:0*/ main__DOT__clock_generator__DOT__times_seven;
|
|
IData/*27:0*/ main__DOT__u_i2cdma__DOT__r_baseaddr;
|
|
IData/*27:0*/ main__DOT__u_i2cdma__DOT__r_memlen;
|
|
IData/*27:0*/ main__DOT__u_i2cdma__DOT__current_addr;
|
|
IData/*31:0*/ main__DOT__u_i2cdma__DOT__next_baseaddr;
|
|
IData/*31:0*/ main__DOT__u_i2cdma__DOT__next_memlen;
|
|
IData/*26:0*/ main__DOT__u_fan__DOT__tach_count;
|
|
IData/*26:0*/ main__DOT__u_fan__DOT__tach_counter;
|
|
IData/*26:0*/ main__DOT__u_fan__DOT__tach_timer;
|
|
IData/*16:0*/ main__DOT__u_fan__DOT__trigger_counter;
|
|
IData/*23:0*/ main__DOT__u_fan__DOT__temp_tmp;
|
|
IData/*31:0*/ main__DOT__u_fan__DOT__temp_data;
|
|
IData/*31:0*/ main__DOT__u_fan__DOT__pre_data;
|
|
IData/*31:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_data;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ika;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ikb;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b;
|
|
IData/*25:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg;
|
|
VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w;
|
|
VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w;
|
|
VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w;
|
|
VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg;
|
|
VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d;
|
|
VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d;
|
|
VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d;
|
|
VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg;
|
|
IData/*19:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg;
|
|
IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data;
|
|
IData/*22:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout;
|
|
IData/*27:0*/ main__DOT__i2ci__DOT__pf_jump_addr;
|
|
};
|
|
struct {
|
|
IData/*27:0*/ main__DOT__i2ci__DOT__pf_insn_addr;
|
|
IData/*27:0*/ main__DOT__i2ci__DOT__abort_address;
|
|
IData/*27:0*/ main__DOT__i2ci__DOT__jump_target;
|
|
IData/*31:0*/ main__DOT__i2ci__DOT__bus_read_data;
|
|
IData/*23:0*/ main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0;
|
|
VlWide<16>/*511:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__cache_word;
|
|
VlWide<16>/*511:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted;
|
|
VlWide<16>/*511:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn;
|
|
VlWide<16>/*511:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data;
|
|
VlWide<16>/*511:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data;
|
|
VlWide<16>/*511:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data;
|
|
IData/*31:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ika;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ikb;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b;
|
|
IData/*25:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg;
|
|
VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w;
|
|
VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w;
|
|
VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w;
|
|
VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg;
|
|
VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d;
|
|
VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d;
|
|
VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d;
|
|
VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg;
|
|
IData/*19:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg;
|
|
IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data;
|
|
IData/*22:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout;
|
|
IData/*31:0*/ main__DOT__swic__DOT__sys_data;
|
|
IData/*21:0*/ main__DOT__swic__DOT__cpu_addr;
|
|
IData/*31:0*/ main__DOT__swic__DOT__sys_idata;
|
|
IData/*31:0*/ main__DOT__swic__DOT__dbg_idata;
|
|
IData/*31:0*/ main__DOT__swic__DOT__dbg_odata;
|
|
IData/*31:0*/ main__DOT__swic__DOT__cmd_wdata;
|
|
IData/*21:0*/ main__DOT__swic__DOT__r_wdbus_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__pic_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__dmac_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ctri_data;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__cpu_idata;
|
|
IData/*31:0*/ main__DOT__swic__DOT__dbg_cpu_status;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data;
|
|
};
|
|
struct {
|
|
IData/*30:0*/ main__DOT__swic__DOT__u_watchdog__DOT__r_value;
|
|
IData/*30:0*/ main__DOT__swic__DOT__u_timer_a__DOT__r_value;
|
|
IData/*30:0*/ main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count;
|
|
IData/*30:0*/ main__DOT__swic__DOT__u_timer_b__DOT__r_value;
|
|
IData/*30:0*/ main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count;
|
|
IData/*30:0*/ main__DOT__swic__DOT__u_timer_c__DOT__r_value;
|
|
IData/*30:0*/ main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count;
|
|
IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__r_counter;
|
|
IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__int_when;
|
|
IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__new_when;
|
|
IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__till_wb;
|
|
IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__till_when;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_request_address;
|
|
IData/*21:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_addr;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_wdata;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_result;
|
|
IData/*21:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v;
|
|
IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv;
|
|
IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc;
|
|
IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_lock_pc;
|
|
IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim_immv;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_addr;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks;
|
|
IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword;
|
|
IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I;
|
|
IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_brev_result;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc;
|
|
IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup;
|
|
IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup;
|
|
IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup;
|
|
IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache;
|
|
IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted;
|
|
};
|
|
struct {
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__ik;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata;
|
|
IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag;
|
|
IData/*21:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr;
|
|
IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag;
|
|
IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted;
|
|
IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr;
|
|
IData/*21:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr;
|
|
IData/*21:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data;
|
|
VlWide<17>/*519:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data;
|
|
IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src;
|
|
IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst;
|
|
IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len;
|
|
IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen;
|
|
IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr;
|
|
IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg;
|
|
VlWide<32>/*1023:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg;
|
|
IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__ik;
|
|
IData/*28:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr;
|
|
VlWide<32>/*1023:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data;
|
|
VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data;
|
|
VlWide<4>/*127:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel;
|
|
VlWide<4>/*127:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel;
|
|
IData/*31:0*/ main__DOT__i2cscopei__DOT__o_bus_data;
|
|
IData/*19:0*/ main__DOT__i2cscopei__DOT__br_holdoff;
|
|
IData/*19:0*/ main__DOT__i2cscopei__DOT__holdoff_counter;
|
|
IData/*30:0*/ main__DOT__i2cscopei__DOT__ck_addr;
|
|
IData/*30:0*/ main__DOT__i2cscopei__DOT__qd_data;
|
|
IData/*30:0*/ main__DOT__i2cscopei__DOT__lst_val;
|
|
IData/*30:0*/ main__DOT__i2cscopei__DOT__imm_val;
|
|
IData/*31:0*/ main__DOT__i2cscopei__DOT__r_data;
|
|
IData/*31:0*/ main__DOT__i2cscopei__DOT__nxt_mem;
|
|
IData/*18:0*/ main__DOT__genbus__DOT__r_wdt_timer;
|
|
IData/*31:0*/ main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k;
|
|
IData/*24:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr;
|
|
IData/*31:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr;
|
|
IData/*31:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword;
|
|
IData/*31:0*/ main__DOT__genbus__DOT__runwb__DOT__wide_addr;
|
|
IData/*29:0*/ main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word;
|
|
IData/*31:0*/ main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k;
|
|
IData/*21:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter;
|
|
IData/*31:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__cword;
|
|
IData/*31:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k;
|
|
IData/*24:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_ctr;
|
|
IData/*21:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr;
|
|
VlWide<16>/*511:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data;
|
|
VlWide<16>/*511:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data;
|
|
};
|
|
struct {
|
|
IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout;
|
|
IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout;
|
|
IData/*19:0*/ __Vdly__main__DOT__emmcscopei__DOT__holdoff_counter;
|
|
IData/*30:0*/ __Vdly__main__DOT__emmcscopei__DOT__ck_addr;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__emmcscopei__DOT__mem__v0;
|
|
IData/*19:0*/ __Vdly__main__DOT__sdioscopei__DOT__holdoff_counter;
|
|
IData/*30:0*/ __Vdly__main__DOT__sdioscopei__DOT__ck_addr;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__sdioscopei__DOT__mem__v0;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v0;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v1;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v2;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v3;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v4;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v5;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v6;
|
|
IData/*21:0*/ __Vdly__main__DOT__wbwide_i2cdma_addr;
|
|
IData/*26:0*/ __Vdly__main__DOT__u_fan__DOT__tach_counter;
|
|
IData/*26:0*/ __Vdly__main__DOT__u_fan__DOT__tach_timer;
|
|
IData/*16:0*/ __Vdly__main__DOT__u_fan__DOT__trigger_counter;
|
|
IData/*23:0*/ __Vdly__main__DOT__u_fan__DOT__temp_tmp;
|
|
IData/*25:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter;
|
|
VlWide<4>/*127:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg;
|
|
VlWide<8>/*255:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg;
|
|
IData/*31:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg;
|
|
IData/*19:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg;
|
|
IData/*22:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout;
|
|
IData/*27:0*/ __Vdly__main__DOT__i2ci__DOT__pf_jump_addr;
|
|
IData/*21:0*/ __Vdly__main__DOT__wbwide_i2cm_addr;
|
|
VlWide<16>/*511:0*/ __Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn;
|
|
IData/*27:0*/ __Vdly__main__DOT__i2ci__DOT__pf_insn_addr;
|
|
IData/*25:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter;
|
|
VlWide<4>/*127:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg;
|
|
VlWide<8>/*255:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg;
|
|
IData/*31:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg;
|
|
IData/*19:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg;
|
|
IData/*22:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout;
|
|
IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value;
|
|
IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value;
|
|
IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value;
|
|
IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__u_jiffies__DOT__r_counter;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__u_jiffies__DOT__int_when;
|
|
IData/*21:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr;
|
|
VlWide<16>/*511:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data;
|
|
IData/*27:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length;
|
|
IData/*27:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr;
|
|
IData/*27:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr;
|
|
VlWide<32>/*1023:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg;
|
|
VlWide<17>/*519:0*/ __Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0;
|
|
VlWide<16>/*511:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg;
|
|
IData/*19:0*/ __Vdly__main__DOT__i2cscopei__DOT__holdoff_counter;
|
|
IData/*30:0*/ __Vdly__main__DOT__i2cscopei__DOT__ck_addr;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__i2cscopei__DOT__mem__v0;
|
|
IData/*18:0*/ __Vdly__main__DOT__genbus__DOT__r_wdt_timer;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0;
|
|
IData/*31:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr;
|
|
};
|
|
struct {
|
|
IData/*29:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word;
|
|
IData/*21:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0;
|
|
IData/*31:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks;
|
|
IData/*27:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor;
|
|
IData/*31:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result;
|
|
IData/*21:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr;
|
|
IData/*18:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag;
|
|
IData/*21:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr;
|
|
IData/*18:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0;
|
|
IData/*31:0*/ __VstlIterCount;
|
|
IData/*31:0*/ __VicoIterCount;
|
|
IData/*31:0*/ __VactIterCount;
|
|
VL_IN64(i_ddr3_controller_iserdes_dqs,63,0);
|
|
VL_IN64(i_ddr3_controller_iserdes_bitslip_reference,63,0);
|
|
VL_OUT64(o_ddr3_controller_dm,63,0);
|
|
QData/*63:0*/ main__DOT__wbwide_i2cdma_sel;
|
|
QData/*47:0*/ main__DOT____Vcellout__wb32_xbar__o_ssel;
|
|
QData/*63:0*/ main__DOT____Vcellout__wbu_xbar__o_sdata;
|
|
QData/*53:0*/ main__DOT____Vcellout__wbu_xbar__o_saddr;
|
|
QData/*44:0*/ main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data;
|
|
QData/*44:0*/ main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data;
|
|
QData/*36:0*/ main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data;
|
|
QData/*44:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data;
|
|
QData/*63:0*/ main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data;
|
|
QData/*63:0*/ main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data;
|
|
QData/*36:0*/ main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data;
|
|
QData/*63:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data;
|
|
QData/*63:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_dm;
|
|
QData/*63:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned;
|
|
QData/*39:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_store;
|
|
QData/*63:0*/ main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel;
|
|
QData/*47:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg;
|
|
QData/*39:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg;
|
|
QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w;
|
|
QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w;
|
|
QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w;
|
|
QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg;
|
|
QData/*63:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel;
|
|
QData/*63:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel;
|
|
QData/*47:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg;
|
|
QData/*39:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg;
|
|
QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w;
|
|
QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w;
|
|
QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w;
|
|
QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg;
|
|
QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result;
|
|
QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result;
|
|
QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result;
|
|
QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result;
|
|
QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_smpy_result;
|
|
QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_umpy_result;
|
|
QData/*62:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend;
|
|
QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff;
|
|
QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel;
|
|
QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel;
|
|
QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel;
|
|
QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel;
|
|
QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel;
|
|
QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel;
|
|
QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__in_word;
|
|
};
|
|
struct {
|
|
QData/*35:0*/ main__DOT__genbus__DOT__ififo_codword;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__exec_word;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__ofifo_codword;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__getinput__DOT__cw_word;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__cw_codword;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word;
|
|
QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword;
|
|
QData/*63:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel;
|
|
QData/*63:0*/ __Vdly__main__DOT__wbwide_i2cdma_sel;
|
|
QData/*47:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg;
|
|
QData/*39:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg;
|
|
QData/*63:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg;
|
|
QData/*47:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg;
|
|
QData/*39:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg;
|
|
QData/*63:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg;
|
|
QData/*35:0*/ __Vdlyvval__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0;
|
|
QData/*35:0*/ __Vdlyvval__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0;
|
|
QData/*62:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend;
|
|
VlUnpacked<CData/*3:0*/, 4> main__DOT__wbwide_xbar__DOT__request;
|
|
VlUnpacked<CData/*2:0*/, 4> main__DOT__wbwide_xbar__DOT__requested;
|
|
VlUnpacked<CData/*3:0*/, 4> main__DOT__wbwide_xbar__DOT__grant;
|
|
VlUnpacked<CData/*5:0*/, 4> main__DOT__wbwide_xbar__DOT__w_mpending;
|
|
VlUnpacked<CData/*1:0*/, 4> main__DOT__wbwide_xbar__DOT__mindex;
|
|
VlUnpacked<CData/*1:0*/, 4> main__DOT__wbwide_xbar__DOT__sindex;
|
|
VlUnpacked<IData/*21:0*/, 4> main__DOT__wbwide_xbar__DOT__m_addr;
|
|
VlUnpacked<VlWide<16>/*511:0*/, 4> main__DOT__wbwide_xbar__DOT__m_data;
|
|
VlUnpacked<QData/*63:0*/, 4> main__DOT__wbwide_xbar__DOT__m_sel;
|
|
VlUnpacked<VlWide<16>/*511:0*/, 4> main__DOT__wbwide_xbar__DOT__s_data;
|
|
VlUnpacked<SData/*12:0*/, 1> main__DOT__wb32_xbar__DOT__request;
|
|
VlUnpacked<SData/*11:0*/, 1> main__DOT__wb32_xbar__DOT__requested;
|
|
VlUnpacked<SData/*12:0*/, 1> main__DOT__wb32_xbar__DOT__grant;
|
|
VlUnpacked<CData/*5:0*/, 1> main__DOT__wb32_xbar__DOT__w_mpending;
|
|
VlUnpacked<CData/*3:0*/, 1> main__DOT__wb32_xbar__DOT__mindex;
|
|
VlUnpacked<CData/*0:0*/, 16> main__DOT__wb32_xbar__DOT__sindex;
|
|
VlUnpacked<CData/*7:0*/, 1> main__DOT__wb32_xbar__DOT__m_addr;
|
|
VlUnpacked<IData/*31:0*/, 1> main__DOT__wb32_xbar__DOT__m_data;
|
|
VlUnpacked<CData/*3:0*/, 1> main__DOT__wb32_xbar__DOT__m_sel;
|
|
VlUnpacked<IData/*31:0*/, 16> main__DOT__wb32_xbar__DOT__s_data;
|
|
VlUnpacked<CData/*2:0*/, 1> main__DOT__wbu_xbar__DOT__request;
|
|
VlUnpacked<CData/*1:0*/, 1> main__DOT__wbu_xbar__DOT__requested;
|
|
VlUnpacked<CData/*2:0*/, 1> main__DOT__wbu_xbar__DOT__grant;
|
|
VlUnpacked<CData/*5:0*/, 1> main__DOT__wbu_xbar__DOT__w_mpending;
|
|
VlUnpacked<CData/*1:0*/, 1> main__DOT__wbu_xbar__DOT__mindex;
|
|
VlUnpacked<CData/*0:0*/, 4> main__DOT__wbu_xbar__DOT__sindex;
|
|
VlUnpacked<IData/*26:0*/, 1> main__DOT__wbu_xbar__DOT__m_addr;
|
|
VlUnpacked<IData/*31:0*/, 1> main__DOT__wbu_xbar__DOT__m_data;
|
|
VlUnpacked<CData/*3:0*/, 1> main__DOT__wbu_xbar__DOT__m_sel;
|
|
VlUnpacked<IData/*31:0*/, 4> main__DOT__wbu_xbar__DOT__s_data;
|
|
VlUnpacked<IData/*31:0*/, 4096> main__DOT__emmcscopei__DOT__mem;
|
|
VlUnpacked<IData/*31:0*/, 4096> main__DOT__sdioscopei__DOT__mem;
|
|
VlUnpacked<SData/*13:0*/, 8> main__DOT__ddr3_controller_inst__DOT__bank_active_row_q;
|
|
VlUnpacked<SData/*13:0*/, 8> main__DOT__ddr3_controller_inst__DOT__bank_active_row_d;
|
|
VlUnpacked<QData/*63:0*/, 2> main__DOT__ddr3_controller_inst__DOT__stage2_dm;
|
|
VlUnpacked<VlWide<16>/*511:0*/, 2> main__DOT__ddr3_controller_inst__DOT__stage2_data;
|
|
VlUnpacked<QData/*63:0*/, 8> main__DOT__ddr3_controller_inst__DOT__unaligned_data;
|
|
VlUnpacked<CData/*7:0*/, 8> main__DOT__ddr3_controller_inst__DOT__unaligned_dm;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q;
|
|
};
|
|
struct {
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d;
|
|
VlUnpacked<IData/*23:0*/, 4> main__DOT__ddr3_controller_inst__DOT__cmd_d;
|
|
VlUnpacked<CData/*3:0*/, 8> main__DOT__ddr3_controller_inst__DOT__added_read_pipe;
|
|
VlUnpacked<CData/*1:0*/, 5> main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q;
|
|
VlUnpacked<CData/*1:0*/, 5> main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d;
|
|
VlUnpacked<SData/*15:0*/, 2> main__DOT__ddr3_controller_inst__DOT__delay_read_pipe;
|
|
VlUnpacked<VlWide<16>/*511:0*/, 2> main__DOT__ddr3_controller_inst__DOT__o_wb_data_q;
|
|
VlUnpacked<CData/*1:0*/, 16> main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q;
|
|
VlUnpacked<CData/*6:0*/, 8> main__DOT__ddr3_controller_inst__DOT__data_start_index;
|
|
VlUnpacked<CData/*4:0*/, 8> main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein;
|
|
VlUnpacked<CData/*4:0*/, 8> main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein;
|
|
VlUnpacked<CData/*4:0*/, 8> main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein;
|
|
VlUnpacked<CData/*4:0*/, 8> main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein;
|
|
VlUnpacked<VlWide<16>/*511:0*/, 16384> main__DOT__bkrami__DOT__mem;
|
|
VlUnpacked<IData/*31:0*/, 8> main__DOT__clock_generator__DOT__counter;
|
|
VlUnpacked<IData/*31:0*/, 1024> main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a;
|
|
VlUnpacked<IData/*31:0*/, 1024> main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b;
|
|
VlUnpacked<CData/*4:0*/, 32> main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem;
|
|
VlUnpacked<IData/*31:0*/, 1024> main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a;
|
|
VlUnpacked<IData/*31:0*/, 1024> main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b;
|
|
VlUnpacked<CData/*0:0*/, 16> main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat;
|
|
VlUnpacked<CData/*6:0*/, 64> main__DOT__console__DOT__rxfifo__DOT__fifo;
|
|
VlUnpacked<CData/*6:0*/, 64> main__DOT__console__DOT__txfifo__DOT__fifo;
|
|
VlUnpacked<IData/*31:0*/, 32> main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset;
|
|
VlUnpacked<VlWide<16>/*511:0*/, 64> main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache;
|
|
VlUnpacked<SData/*15:0*/, 8> main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags;
|
|
VlUnpacked<IData/*18:0*/, 8> main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags;
|
|
VlUnpacked<VlWide<16>/*511:0*/, 64> main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem;
|
|
VlUnpacked<SData/*11:0*/, 16> main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data;
|
|
VlUnpacked<VlWide<17>/*519:0*/, 16> main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem;
|
|
VlUnpacked<IData/*31:0*/, 1024> main__DOT__i2cscopei__DOT__mem;
|
|
VlUnpacked<CData/*6:0*/, 128> main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__remap;
|
|
VlUnpacked<IData/*31:0*/, 256> main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl;
|
|
VlUnpacked<CData/*6:0*/, 128> main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__remap;
|
|
VlUnpacked<IData/*31:0*/, 1024> main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl;
|
|
VlUnpacked<QData/*35:0*/, 64> main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo;
|
|
VlUnpacked<QData/*35:0*/, 1024> main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo;
|
|
VlUnpacked<CData/*3:0*/, 32> main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem;
|
|
VlUnpacked<CData/*0:0*/, 7> __Vm_traceActivity;
|
|
};
|
|
VlTriggerVec<1> __VstlTriggered;
|
|
VlTriggerVec<1> __VicoTriggered;
|
|
VlTriggerVec<9> __VactTriggered;
|
|
VlTriggerVec<9> __VnbaTriggered;
|
|
|
|
// INTERNAL VARIABLES
|
|
Vmain__Syms* const vlSymsp;
|
|
|
|
// CONSTRUCTORS
|
|
Vmain___024root(Vmain__Syms* symsp, const char* v__name);
|
|
~Vmain___024root();
|
|
VL_UNCOPYABLE(Vmain___024root);
|
|
|
|
// INTERNAL METHODS
|
|
void __Vconfigure(bool first);
|
|
};
|
|
|
|
|
|
#endif // guard
|