UberDDR3/rtl
AngeloJacobo c81f9044d8 add activate-to-activate delay, calibrate-able for both late-write-dq and early-read-dq, simulation passing for ddr3-1600! 2025-01-30 19:07:09 +08:00
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axi added self-refresh to vivado IP GUI, tested self-refresh on hardware with microblaze 2024-11-24 17:40:21 +08:00
ecc Revert "add self-refresh option, passing Simulation, ongoing formal" 2024-11-23 11:43:05 +08:00
spd added simulation and project demo with XADC 2025-01-12 14:55:43 +08:00
ddr3_controller.v add activate-to-activate delay, calibrate-able for both late-write-dq and early-read-dq, simulation passing for ddr3-1600! 2025-01-30 19:07:09 +08:00
ddr3_phy.v update copyright date 2025-01-02 13:18:42 +08:00
ddr3_top.v update copyright date 2025-01-02 13:18:42 +08:00