21 lines
1.7 KiB
Plaintext
21 lines
1.7 KiB
Plaintext
IDELAYCTRL_model.v,verilog,xil_defaultlib,../../testbench/models/IDELAYCTRL_model.v,incdir="../../testbench"
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IDELAYE2_model.v,verilog,xil_defaultlib,../../testbench/models/IDELAYE2_model.v,incdir="../../testbench"
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IOBUF_DCIEN.v,verilog,xil_defaultlib,../../testbench/models/IOBUF_DCIEN.v,incdir="../../testbench"
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IOBUF_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUF_model.v,incdir="../../testbench"
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IOBUFDS_DCIEN_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUFDS_DCIEN_model.v,incdir="../../testbench"
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IOBUFDS_model.v,verilog,xil_defaultlib,../../testbench/models/IOBUFDS_model.v,incdir="../../testbench"
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ISERDESE2_model.v,verilog,xil_defaultlib,../../testbench/models/ISERDESE2_model.v,incdir="../../testbench"
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OBUFDS_model.v,verilog,xil_defaultlib,../../testbench/models/OBUFDS_model.v,incdir="../../testbench"
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ODELAYE2_model.v,verilog,xil_defaultlib,../../testbench/models/ODELAYE2_model.v,incdir="../../testbench"
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OSERDESE2_model.v,verilog,xil_defaultlib,../../testbench/models/OSERDESE2_model.v,incdir="../../testbench"
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OBUF_model.v,verilog,xil_defaultlib,../../testbench/models/OBUF_model.v,incdir="../../testbench"
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ddr3_controller.v,verilog,xil_defaultlib,../../rtl/ddr3_controller.v,incdir="../../testbench"
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ddr3_phy.v,verilog,xil_defaultlib,../../rtl/ddr3_phy.v,incdir="../../testbench"
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ddr3_top.v,verilog,xil_defaultlib,../../rtl/ddr3_top.v,incdir="../../testbench"
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ddr3.sv,systemverilog,xil_defaultlib,../../testbench/ddr3.sv,incdir="../../testbench"
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ddr3_module.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_module.sv,incdir="../../testbench"
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ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_dimm_micron_sim.sv,incdir="../../testbench"
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glbl.v,Verilog,xil_defaultlib
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