UberDDR3/rtl
AngeloJacobo b3ab21a6d5 add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY) 2023-08-15 19:12:49 +08:00
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ddr3_controller.v add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY) 2023-08-15 19:12:49 +08:00
ddr3_phy.v correct generate indexes 2023-08-04 07:52:31 +08:00
ddr3_top.v fixed localparam value for wb_addr_bits 2023-08-04 07:53:12 +08:00
fwb_slave.v make stall and accessible outside, removed added assumptions with i_slave_busy 2023-07-13 18:48:34 +08:00