UberDDR3/example_demo/arty_s7
AngeloJacobo 0ca641799d add bit files for example demo 2024-06-10 16:44:41 +08:00
..
Arty-S7-50-Master.xdc clean repo 2024-06-09 11:31:58 +08:00
arty_ddr3.bit add bit files for example demo 2024-06-10 16:44:41 +08:00
arty_ddr3.v replace clock wizard with PLL 2024-06-09 15:31:27 +08:00
clk_wiz.v replace clock wizard with PLL 2024-06-09 15:31:27 +08:00
uart.v clean repo 2024-06-09 11:31:58 +08:00
uart_rx.v clean repo 2024-06-09 11:31:58 +08:00
uart_tx.v clean repo 2024-06-09 11:31:58 +08:00