UberDDR3/testbench/xsim/vlog.prj

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verilog xil_defaultlib --include "../" \
"../../rtl/ddr3_controller.v" \
"../../rtl/ddr3_phy.v" \
"../../rtl/ddr3_top.v" \
sv xil_defaultlib --include "../" \
"../ddr3.sv" \
"../../rtl/ecc/ecc_dec.sv" \
"../../rtl/ecc/ecc_enc.sv" \
"../ddr3_dimm_micron_sim.sv" \
"../ddr3_module.sv" \
verilog xil_defaultlib "glbl.v"
nosort