UberDDR3/rtl
AngeloJacobo e9f1ab4971 modify debug port logic for wbscope 2023-08-04 07:57:09 +08:00
..
ddr3_controller.v modify debug port logic for wbscope 2023-08-04 07:57:09 +08:00
ddr3_phy.v correct generate indexes 2023-08-04 07:52:31 +08:00
ddr3_top.v fixed localparam value for wb_addr_bits 2023-08-04 07:53:12 +08:00
fwb_slave.v make stall and accessible outside, removed added assumptions with i_slave_busy 2023-07-13 18:48:34 +08:00