117 lines
3.3 KiB
Makefile
117 lines
3.3 KiB
Makefile
PROJECT = arty_ddr3
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BOARD = arty_s7_50
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FAMILY = spartan7
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PART = xc7s50csga324-1
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CHIPDB = ${SPARTAN7_CHIPDB}
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ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v ../../rtl/ddr3_phy.v ../../rtl/ddr3_top.v uart_rx.v uart_tx.v clk_wiz.v
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#############################################################################################
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NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
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NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
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PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
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DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
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SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
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CHIPDB ?= ./
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ifeq ($(CHIPDB),)
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CHIPDB = ./
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endif
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PYPY3 ?= pypy3
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TOP ?= ${PROJECT}
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TOP_MODULE ?= ${TOP}
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TOP_VERILOG ?= ${TOP}.v
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PNR_DEBUG ?= # --verbose --debug
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JTAG_LINK ?= --board ${BOARD}
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XDC ?= ${PROJECT}.xdc
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.PHONY: openxc7
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openxc7: ${PROJECT}_openxc7.bit
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.PHONY: program
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program: ${PROJECT}_openxc7.bit
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openFPGALoader ${JTAG_LINK} --bitstream $<
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${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
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yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
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# The chip database only needs to be generated once
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# that is why we don't clean it with make clean
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${CHIPDB}/${DBPART}.bin:
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${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
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bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
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rm -f ${DBPART}.bba
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${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
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nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
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${PROJECT}.frames: ${PROJECT}.fasm
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fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
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${PROJECT}_openxc7.bit: ${PROJECT}.frames
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xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
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#############################################################################################
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# SPDX-License-Identifier: MIT
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# Generated from https://github.com/FPGAOL-CE/caas-wizard
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#
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BUILDDIR := ${CURDIR}/build
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LOGFILE := ${BUILDDIR}/top.log
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# Build design
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.PHONY: vivado
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vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
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${BUILDDIR}:
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mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
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.ONESHELL:
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${BUILDDIR}/vivado.tcl: ${BUILDDIR}
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cat << EOF > $@
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# vivado.tcl generated for FPGAOL-CE/caas-wizard
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# can be launched from any directory
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cd ${BUILDDIR}
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create_project -part ${PART} -force v_proj
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set_property target_language Verilog [current_project]
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cd ..
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read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
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read_xdc [glob $(wildcard ${PROJECT}_vivado.xdc) ]
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cd build
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synth_design -top ${PROJECT}
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opt_design
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place_design
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phys_opt_design
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route_design
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write_bitstream -verbose -force ${PROJECT}_vivado.bit
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# report_utilization -file util.rpt
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# report_timing_summary -file timing.rpt
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EOF
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${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
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cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
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.PHONY: program_vivado
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program_vivado:
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openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
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#############################################################################################
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.PHONY: clean
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clean:
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rm -f *.bit
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rm -f *.frames
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rm -f *.fasm
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rm -f *.json
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rm -f *.bin
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rm -f *.bba
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rm -rf ${BUILDDIR}
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