AngeloJacobo 9769a7cfaa pass formal for 8-lane config and pass verilator linting		2023-08-20 11:07:22 +08:00
..
ddr3_controller.v	pass formal for 8-lane config and pass verilator linting	2023-08-20 11:07:22 +08:00
ddr3_phy.v	add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)	2023-08-15 19:35:44 +08:00
ddr3_top.v	add option for ODELAY_SUPPORTED=0 and added port for i_ddr3_clk_90	2023-08-15 19:37:28 +08:00
fwb_slave.v	make stall and accessible outside, removed added assumptions with i_slave_busy	2023-07-13 18:48:34 +08:00