18 lines
286 B
Verilog
Executable File
18 lines
286 B
Verilog
Executable File
`timescale 1 ps / 1 ps
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module IOBUFDS_DCIEN_model #(
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parameter IBUF_LOW_PWR = "TRUE",
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parameter SLEW = "SLOW",
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parameter USE_IBUFDISABLE = "TRUE"
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)(
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output O,
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inout IO,
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inout IOB,
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input DCITERMDISABLE,
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input I,
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input IBUFDISABLE,
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input T
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);
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// black box
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endmodule
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