42 lines
2.8 KiB
C++
42 lines
2.8 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Symbol table implementation internals
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#include "Vmain__Syms.h"
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#include "Vmain.h"
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#include "Vmain___024root.h"
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// FUNCTIONS
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Vmain__Syms::~Vmain__Syms()
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{
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}
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Vmain__Syms::Vmain__Syms(VerilatedContext* contextp, const char* namep, Vmain* modelp)
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: VerilatedSyms{contextp}
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// Setup internal state of the Syms class
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, __Vm_modelp{modelp}
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// Setup module instances
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, TOP{this, namep}
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{
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// Configure time unit / time precision
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_vm_contextp__->timeunit(-12);
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_vm_contextp__->timeprecision(-12);
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// Setup each module's pointers to their submodules
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// Setup each module's pointer back to symbol table (for public functions)
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TOP.__Vconfigure(true);
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// Setup scopes
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__Vscope_main__swic__thecpu__core.configure(this, name(), "main.swic.thecpu.core", "core", 0, VerilatedScope::SCOPE_OTHER);
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__Vscope_main__swic__thecpu__core__instruction_decoder.configure(this, name(), "main.swic.thecpu.core.instruction_decoder", "instruction_decoder", 0, VerilatedScope::SCOPE_OTHER);
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// Setup export functions
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for (int __Vfinal = 0; __Vfinal < 2; ++__Vfinal) {
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__Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"alu_ce", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0);
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__Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"alu_sim", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0);
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__Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"alu_sim_immv", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,22,0);
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__Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"dcd_pc", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,27,0);
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__Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"op_sim", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0);
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__Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"op_sim_immv", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,22,0);
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__Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"op_valid", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0);
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__Vscope_main__swic__thecpu__core__instruction_decoder.varInsert(__Vfinal,"o_sim", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0);
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__Vscope_main__swic__thecpu__core__instruction_decoder.varInsert(__Vfinal,"o_sim_immv", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,22,0);
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}
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}
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