14 lines
893 B
Plaintext
14 lines
893 B
Plaintext
verilog xil_defaultlib --include "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl" --include "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench" \
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"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" \
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"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" \
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"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" \
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sv xil_defaultlib --include "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl" --include "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench" \
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"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" \
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"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" \
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"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" \
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verilog xil_defaultlib "/home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/glbl.v"
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nosort
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