11374 lines
1.8 MiB
11374 lines
1.8 MiB
#-----------------------------------------------------------
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# xsim v2021.2 (64-bit)
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# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
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# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
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# Start of session at: Wed Jul 5 15:49:42 2023
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# Process ID: 11039
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# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
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# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
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# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
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# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
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# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3693.322 MHz, CPU Physical cores: 2, Host memory: 7450 MB
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#-----------------------------------------------------------
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source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
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# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
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Time resolution is 1 ps
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source cmd.tcl
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## set curr_wave [current_wave_config]
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## if { [string length $curr_wave] == 0 } {
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## if { [llength [get_objects]] > 0} {
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## add_wave /
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## set_property needs_save false [current_wave_config]
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## } else {
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## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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## }
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## }
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## run -all
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Test ns_to_cycles() function:
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ns_to_cycles(15) = 3 = 2 [exact]
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ns_to_cycles(14.5) = 3 = 2 [round-off]
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ns_to_cycles(11) = 3 = 2 [round-up]
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Test nCK_to_cycles() function:
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ns_to_cycles(16) = 4 = 4 [exact]
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ns_to_cycles(15) = 4 = 4 [round-off]
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ns_to_cycles(13) = 4 = 4 [round-up]
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Test ns_to_nCK() function:
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ns_to_cycles(15) = 12 = 6 [exact]
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ns_to_cycles(14.875) = 12 = 6 [round-off]
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ns_to_cycles(13.875) = 12 = 6 [round-up]
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ns_to_nCK(tRCD) = 11 = 6 [WRONG]
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tRTP = 7.5 = 10.000000
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ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test $floor() function:
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$floor(5/2) = 2.5 = 2
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$floor(9/4) = 2.25 = 2
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$floor(9/4) = 2 = 2
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$floor(9/5) = 1.8 = 1
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DELAY_COUNTER_WIDTH = 16
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DELAY_SLOT_WIDTH = 19
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serdes_ratio = 4
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wb_addr_bits = 24
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wb_data_bits = 512
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wb_sel_bits = 64
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READ_SLOT = 2
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WRITE_SLOT = 3
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ACTIVATE_SLOT = 0
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PRECHARGE_SLOT = 1
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DELAYS:
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ns_to_nCK(tRCD): 6
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ns_to_nCK(tRP): 6
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ns_to_nCK(tRTP): 4
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tCCD: 4
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(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
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(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
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(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
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$signed(4'b1100)>>>4: 1111
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PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
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ACTIVATE_TO_WRITE_DELAY = 3 = 0
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ACTIVATE_TO_READ_DELAY = 2 = 0
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READ_TO_WRITE_DELAY = 2 = 1
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READ_TO_READ_DELAY = 0 = 0
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READ_TO_PRECHARGE_DELAY = 1 =1
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WRITE_TO_WRITE_DELAY = 0 = 0
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WRITE_TO_READ_DELAY = 4 = 3
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WRITE_TO_PRECHARGE_DELAY = 5 = 4
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STAGE2_DATA_DEPTH = 2 = 2
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READ_ACK_PIPE_WIDTH = 6
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ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive.
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[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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[510000 ps] NOP -> [370000 ps] MRS ->
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ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
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[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
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[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
|
|
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
|
|
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[327500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67813200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67815700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67818200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67820700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67823200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67825700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67828200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67830700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67833200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67835700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67963200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67965700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67968200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67970700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67973200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67975700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67978200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67980700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67983200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67985700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68113200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68115700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68118200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68120700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68123200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68125700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68128200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68130700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68133200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68135700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68263276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68265776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68268276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68270776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68273276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68275776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68278276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68280776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68283276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68285776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68413354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68415854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68418354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68420854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68423354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68425854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68428354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68430854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68433354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68435854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70214450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70216950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70219450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70221950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70224450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70226950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70229450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70231950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70234450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70236950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70364450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70366950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70369450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70371950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70374450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70376950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70379450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70381950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70384450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70386950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70511950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70514450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70516950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70519450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70521950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70524450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70526950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70529450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70531950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70534450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71863200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71865700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71868200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71870700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71873200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71875700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71878200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71880700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71883200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71885700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72013200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72015700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72018200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72020700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72023200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72025700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72028200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72030700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72033200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72035700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72163200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72165700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72168200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72170700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72173200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72175700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72178200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72180700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72183200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72185700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72313276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72315776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72318276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72320776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72323276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72325776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72328276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72330776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72333276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72335776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72463354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72465854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72468354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72470854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72473354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72475854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72478354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72480854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72483354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72485854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74264450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74266950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74269450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74271950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74274450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74276950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74279450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74281950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74284450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74286950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74414450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74416950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74419450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74421950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74424450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74426950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74429450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74431950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74434450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74436950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74561950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74564450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74566950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74569450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74571950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74574450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74576950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74579450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74581950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74584450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75913200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75915700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75918200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75920700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75923200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75925700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75928200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75930700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75933200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75935700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76063200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76065700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76068200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76070700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76073200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76075700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76078200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76080700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76083200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76085700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76213200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76215700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76218200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76220700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76223200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76225700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76228200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76230700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76233200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76235700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76363276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76365776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76368276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76370776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76373276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76375776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76378276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76380776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76383276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76385776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76513354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76515854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76518354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76520854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76523354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76525854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76528354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76530854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76533354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76535854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78314450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78316950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78319450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78321950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78324450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78326950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78329450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78331950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78334450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78336950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78464450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78466950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78469450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78471950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78474450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78476950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78479450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78481950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78484450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78486950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78611950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78614450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78616950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78619450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78621950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78624450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78626950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78629450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78631950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78634450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79963200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79965700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79968200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79970700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79973200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79975700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79978200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79980700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79983200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79985700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80113200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80115700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80118200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80120700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80123200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80125700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80128200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80130700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80133200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80135700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80263200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80265700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80268200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80270700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80273200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80275700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80278200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80280700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80283200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80285700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80413276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80415776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80418276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80420776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80423276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80425776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80428276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80430776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80433276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80435776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80563354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80565854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80568354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80570854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80573354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80575854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80578354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80580854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80583354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80585854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82364450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82366950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82369450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82371950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82374450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82376950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82379450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82381950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82384450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82386950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82514450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82516950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82519450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82521950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82524450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82526950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82529450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82531950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82534450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82536950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82661950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82664450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82666950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82669450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82671950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82674450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82676950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82679450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82681950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82684450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84013200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84015700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84018200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84020700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84023200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84025700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84028200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84030700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84033200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84035700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84163200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84165700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84168200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84170700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84173200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84175700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84178200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84180700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84183200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84185700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84313200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84315700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84318200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84320700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84323200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84325700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84328200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84330700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84333200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84335700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84463276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84465776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84468276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84470776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84473276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84475776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84478276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84480776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84483276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84485776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84613354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84615854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84618354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84620854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84623354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84625854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84628354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84630854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84633354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84635854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86414450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86416950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86419450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86421950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86424450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86426950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86429450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86431950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86434450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86436950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86564450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86566950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86569450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86571950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86574450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86576950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86579450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86581950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86584450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86586950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86711950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86714450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86716950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86719450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86721950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86724450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86726950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86729450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86731950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86734450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88063200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88065700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88068200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88070700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88073200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88075700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88078200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88080700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88083200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88085700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88213200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88215700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88218200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88220700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88223200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88225700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88228200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88230700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88233200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88235700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88363200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88365700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88368200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88370700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88373200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88375700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88378200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88380700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88383200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88385700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88513276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88515776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88518276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88520776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88523276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88525776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88528276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88530776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88533276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88535776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88663354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88665854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88668354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88670854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88673354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88675854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88678354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88680854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88683354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88685854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90464450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90466950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90469450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90471950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90474450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90476950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90479450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90481950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90484450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90486950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90614450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90616950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90619450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90621950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90624450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90626950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90629450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90631950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90634450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90636950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90761950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90764450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90766950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90769450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90771950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90774450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90776950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90779450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90781950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90784450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92113200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92115700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92118200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92120700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92123200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92125700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92128200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92130700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92133200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92135700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92263200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92265700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92268200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92270700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92273200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92275700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92278200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92280700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92283200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92285700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92413200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92415700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92418200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92420700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92423200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92425700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92428200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92430700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92433200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92435700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92563276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92565776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92568276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92570776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92573276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92575776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92578276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92580776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92583276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92585776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92713354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92715854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92718354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92720854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92723354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92725854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92728354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92730854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92733354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92735854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94514450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94516950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94519450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94521950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94524450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94526950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94529450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94531950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94534450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94536950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94664450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94666950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94669450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94671950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94674450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94676950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94679450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94681950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94684450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94686950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94811950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94814450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94816950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94819450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94821950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94824450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94826950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94829450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94831950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94834450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96163200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96165700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96168200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96170700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96173200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96175700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96178200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96180700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96183200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96185700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96313200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96315700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96318200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96320700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96323200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96325700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96328200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96330700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96333200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96335700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96463200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96465700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96468200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96470700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96473200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96475700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96478200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96480700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96483200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96485700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96613276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96615776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96618276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96620776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96623276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96625776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96628276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96630776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96633276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96635776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96763354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96765854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96768354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96770854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96773354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96775854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96778354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96780854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96783354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96785854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98564450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98566950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98569450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98571950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98574450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98576950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98579450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98581950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98584450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98586950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98714450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98716950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98719450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98721950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98724450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98726950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98729450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98731950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98734450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98736950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98861950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98864450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98866950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98869450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98871950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98874450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98876950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98879450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98881950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98884450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
[32270000 ps] MRS ->
|
|
[10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [37500 ps] ACT @ (0, 0) ->
|
|
[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
|
|
[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
|
|
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
|
|
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
|
|
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
|
|
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
|
|
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
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|
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
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|
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
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|
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
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|
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
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|
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
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|
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
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|
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
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|
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
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|
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
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|
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
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|
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
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|
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
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|
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
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|
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
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|
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
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|
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
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|
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
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|
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
|
|
[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
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|
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
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|
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
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|
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
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|
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
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|
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
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|
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
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|
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
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|
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
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|
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
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|
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
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|
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
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|
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
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|
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
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|
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
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|
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
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|
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
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|
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
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|
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
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|
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
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|
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
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|
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
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|
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
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|
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
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|
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
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|
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) ->
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|
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
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|
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
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|
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
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|
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
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|
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
|
|
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
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|
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
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|
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
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|
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
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|
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
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|
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
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|
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
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|
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
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|
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
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|
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
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|
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
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|
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
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|
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
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|
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
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|
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
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|
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
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|
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
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|
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
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|
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
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|
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
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|
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) ->
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|
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
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|
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
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|
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
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|
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
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|
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
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|
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
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|
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
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|
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
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|
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
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|
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
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|
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
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|
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
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|
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
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|
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
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|
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
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|
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
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|
[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
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|
[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
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|
[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
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|
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
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|
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
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|
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
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|
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
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|
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
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|
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
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|
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
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|
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
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|
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
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|
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
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|
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
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|
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
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|
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
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|
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
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|
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
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|
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
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|
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
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|
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
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|
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
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|
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
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|
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
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|
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
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|
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
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|
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
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|
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
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|
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
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|
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
|
|
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
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|
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
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|
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
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|
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
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|
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
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|
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
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|
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
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|
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
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|
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
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|
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
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|
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
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|
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
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|
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
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|
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
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|
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
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|
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
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|
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
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|
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
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|
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
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|
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
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|
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
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|
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
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|
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
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|
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
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|
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
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|
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
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|
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
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|
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
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|
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [ 5000 ps] NOP ->
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|
[ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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|
[360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) ->
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|
[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
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|
[ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
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|
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
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|
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
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|
[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) ->
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|
[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
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|
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
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|
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
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|
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
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|
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
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|
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
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|
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
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|
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
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|
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
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|
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
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|
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
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|
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
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|
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
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|
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
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|
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
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|
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
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|
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
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|
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
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|
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
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|
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
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|
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
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|
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) ->
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|
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
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|
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
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|
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
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|
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
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|
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
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|
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
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|
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
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|
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
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|
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
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|
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
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|
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
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|
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
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|
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
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|
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
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|
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
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|
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
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|
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
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|
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
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|
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
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|
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
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|
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
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|
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
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|
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
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|
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
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|
[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
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|
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) ->
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|
[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
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|
[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
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|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
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|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
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|
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
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|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
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|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
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|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
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|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
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|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
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|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
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|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
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|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
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|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
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|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
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|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
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|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
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|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
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|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
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|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
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|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
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|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
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|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
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|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
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|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
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|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
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|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
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|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
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|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
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|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
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|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
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|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
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|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
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|
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
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|
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
|
|
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
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|
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
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|
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
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|
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
|
|
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
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|
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
|
|
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
|
|
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
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|
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
|
|
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
|
|
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
|
|
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
|
|
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
|
|
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
|
|
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
|
|
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
|
|
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
|
|
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
|
|
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
|
|
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
|
|
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
|
|
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
|
|
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
|
|
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) ->
|
|
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
|
|
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
|
|
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
|
|
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
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|
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
|
|
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
|
|
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
|
|
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
|
|
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
|
|
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
|
|
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
|
|
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
|
|
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
|
|
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
|
|
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
|
|
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
|
|
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
|
|
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
|
|
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
|
|
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
|
|
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
|
|
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
|
|
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
|
|
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
|
|
[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) ->
|
|
[10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (2, 0) ->
|
|
[15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
|
|
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
|
|
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
|
|
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
|
|
[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) ->
|
|
[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
|
|
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
|
|
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
|
|
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
|
|
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
|
|
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
|
|
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
|
|
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
|
|
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
|
|
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
|
|
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
|
|
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
|
|
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
|
|
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
|
|
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
|
|
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
|
|
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
|
|
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
|
|
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
|
|
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
|
|
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
|
|
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
|
|
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
|
|
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
|
|
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
|
|
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
|
|
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
|
|
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
|
|
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
|
|
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
|
|
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
|
|
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
|
|
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
|
|
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
|
|
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
|
|
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
|
|
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
|
|
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
|
|
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
|
|
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
|
|
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
|
|
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
|
|
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
|
|
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
|
|
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
|
|
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
|
|
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
|
|
[ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
|
|
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
|
|
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
|
|
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
|
|
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
|
|
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
|
|
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
|
|
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
|
|
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
|
|
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
|
|
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
|
|
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
|
|
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
|
|
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
|
|
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
|
|
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
|
|
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
|
|
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
|
|
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
|
|
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
|
|
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
|
|
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
|
|
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
|
|
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
|
|
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
|
|
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) ->
|
|
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
|
|
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
|
|
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
|
|
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
|
|
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
|
|
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
|
|
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
|
|
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
|
|
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
|
|
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
|
|
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
|
|
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
|
|
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
|
|
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
|
|
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
|
|
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
|
|
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
|
|
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
|
|
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
|
|
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
|
|
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
|
|
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
|
|
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
|
|
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
|
|
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
|
|
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) ->
|
|
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
|
|
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
|
|
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
|
|
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
|
|
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
|
|
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
|
|
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
|
|
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
|
|
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
|
|
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
|
|
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
|
|
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
|
|
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
|
|
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
|
|
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
|
|
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
|
|
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
|
|
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
|
|
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
|
|
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
|
|
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
|
|
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
|
|
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
|
|
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
|
|
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
|
|
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
|
|
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
|
|
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
|
|
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
|
|
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
|
|
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
|
|
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
|
|
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
|
|
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
|
|
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
|
|
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
|
|
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
|
|
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
|
|
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
|
|
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
|
|
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
|
|
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
|
|
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
|
|
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
|
|
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
|
|
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
|
|
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
|
|
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
|
|
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
|
|
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
|
|
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
|
|
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: FIRST ROW
|
|
Number of Operations: 2304
|
|
Time Started: 99840 ns
|
|
Time Done: 123930 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) ->
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [27500 ps] NOP -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 124010000.0 ps
|
|
[70000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
|
|
[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
|
|
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
|
|
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
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|
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
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|
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
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|
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
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|
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
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|
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
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|
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
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|
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
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|
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
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|
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
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|
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
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|
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
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|
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
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|
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
|
|
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
|
|
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
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|
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
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|
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
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|
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
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|
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
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|
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
|
|
[ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
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|
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
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|
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
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|
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
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|
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
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|
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
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|
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
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|
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
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|
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
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|
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
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|
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
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|
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
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|
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
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|
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
|
|
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
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|
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
|
|
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
|
|
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
|
|
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
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|
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
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|
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
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|
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
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|
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
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|
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
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|
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
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|
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) ->
|
|
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
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|
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
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|
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
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|
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
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|
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
|
|
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
|
|
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
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|
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
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|
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
|
|
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
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|
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
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|
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
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|
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
|
|
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
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|
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
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|
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
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|
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
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|
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
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|
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
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|
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
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|
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
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|
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
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|
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
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|
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
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|
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
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|
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) ->
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|
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
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|
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
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|
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
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|
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
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|
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
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|
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
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|
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
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|
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
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|
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
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|
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
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|
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
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|
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
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|
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
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|
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
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|
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
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|
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
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|
[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
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|
[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
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|
[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
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|
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
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|
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
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|
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
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|
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
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|
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
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|
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
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|
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
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|
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
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|
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
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|
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
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|
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
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|
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
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|
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
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|
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
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|
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
|
|
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
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|
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
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|
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
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|
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
|
|
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
|
|
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
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|
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
|
|
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
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|
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
|
|
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
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|
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
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|
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
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|
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
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|
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
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|
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
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|
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
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|
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
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|
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
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|
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
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|
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
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|
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
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|
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
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|
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
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|
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
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|
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
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|
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
|
|
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
|
|
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
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|
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
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|
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
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|
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
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|
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
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|
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
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|
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
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|
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
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|
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
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|
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
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|
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
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|
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
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|
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
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|
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) ->
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|
[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) ->
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|
[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
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|
[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
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|
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
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|
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
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|
[10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) ->
|
|
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 96) ->
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|
[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
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|
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
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|
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
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|
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
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|
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
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|
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
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|
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
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|
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
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|
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
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|
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
|
|
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
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|
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
|
|
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
|
|
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
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|
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
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|
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
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|
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
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|
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
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|
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
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|
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
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|
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
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|
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) ->
|
|
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
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|
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
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|
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
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|
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
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|
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
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|
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
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|
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
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|
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
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|
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
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|
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
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|
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
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|
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
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|
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
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|
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
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|
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
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|
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
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|
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
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|
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
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|
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
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|
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
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|
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
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|
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
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|
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
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|
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
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|
[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
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|
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) ->
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|
[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
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|
[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
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|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
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|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
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|
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
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|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
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|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
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|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
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|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
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|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
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|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
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|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
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|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
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|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
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|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
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|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
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|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
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|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
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|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
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|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
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|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
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|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
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|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
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|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
|
|
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
|
|
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
|
|
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
|
|
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
|
|
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
|
|
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
|
|
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
|
|
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
|
|
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
|
|
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
|
|
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
|
|
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
|
|
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
|
|
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
|
|
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
|
|
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
|
|
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
|
|
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
|
|
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
|
|
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
|
|
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
|
|
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
|
|
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
|
|
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
|
|
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) ->
|
|
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
|
|
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
|
|
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
|
|
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
|
|
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
|
|
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
|
|
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
|
|
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
|
|
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
|
|
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
|
|
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
|
|
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
|
|
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
|
|
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
|
|
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
|
|
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
|
|
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
|
|
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
|
|
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
|
|
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
|
|
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
|
|
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
|
|
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
|
|
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
|
|
[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) ->
|
|
[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
|
|
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
|
|
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
|
|
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
|
|
[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP ->
|
|
[ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> [30000 ps] REF ->
|
|
[360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
|
|
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
|
|
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
|
|
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
|
|
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
|
|
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
|
|
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
|
|
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
|
|
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
|
|
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
|
|
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
|
|
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
|
|
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
|
|
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
|
|
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
|
|
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
|
|
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
|
|
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
|
|
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
|
|
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
|
|
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
|
|
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
|
|
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
|
|
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
|
|
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
|
|
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
|
|
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
|
|
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
|
|
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
|
|
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
|
|
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
|
|
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
|
|
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
|
|
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
|
|
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
|
|
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
|
|
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
|
|
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
|
|
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
|
|
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
|
|
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
|
|
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
|
|
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
|
|
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
|
|
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
|
|
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
|
|
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
|
|
[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
|
|
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
|
|
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
|
|
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
|
|
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
|
|
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
|
|
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
|
|
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
|
|
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
|
|
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
|
|
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
|
|
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
|
|
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
|
|
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
|
|
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
|
|
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
|
|
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
|
|
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
|
|
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
|
|
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
|
|
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
|
|
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
|
|
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
|
|
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
|
|
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
|
|
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) ->
|
|
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
|
|
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
|
|
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
|
|
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
|
|
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
|
|
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
|
|
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
|
|
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
|
|
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
|
|
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
|
|
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
|
|
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
|
|
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
|
|
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
|
|
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
|
|
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
|
|
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
|
|
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
|
|
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
|
|
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
|
|
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
|
|
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
|
|
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
|
|
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
|
|
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
|
|
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) ->
|
|
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
|
|
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
|
|
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
|
|
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
|
|
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
|
|
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
|
|
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
|
|
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
|
|
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
|
|
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
|
|
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
|
|
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
|
|
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
|
|
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
|
|
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
|
|
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
|
|
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
|
|
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
|
|
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
|
|
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
|
|
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
|
|
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
|
|
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
|
|
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
|
|
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
|
|
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
|
|
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
|
|
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
|
|
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
|
|
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
|
|
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
|
|
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
|
|
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
|
|
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
|
|
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
|
|
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
|
|
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
|
|
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
|
|
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
|
|
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
|
|
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
|
|
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
|
|
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
|
|
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
|
|
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
|
|
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
|
|
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
|
|
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
|
|
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
|
|
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
|
|
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
|
|
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: MIDDLE ROW
|
|
Number of Operations: 2304
|
|
Time Started: 124030 ns
|
|
Time Done: 148520 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) ->
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 148600000.0 ps
|
|
[97500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) ->
|
|
[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
|
|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
|
|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
|
|
[10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) ->
|
|
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 152) ->
|
|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
|
|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
|
|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
|
|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
|
|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
|
|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
|
|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
|
|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
|
|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
|
|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
|
|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
|
|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
|
|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
|
|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) ->
|
|
[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) ->
|
|
[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) ->
|
|
[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) ->
|
|
[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) ->
|
|
[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) ->
|
|
[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) ->
|
|
[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) ->
|
|
[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) ->
|
|
[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) ->
|
|
[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) ->
|
|
[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) ->
|
|
[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) ->
|
|
[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) ->
|
|
[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) ->
|
|
[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) ->
|
|
[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) ->
|
|
[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) ->
|
|
[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) ->
|
|
[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) ->
|
|
[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) ->
|
|
[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) ->
|
|
[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) ->
|
|
[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) ->
|
|
[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) ->
|
|
[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) ->
|
|
[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) ->
|
|
[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) ->
|
|
[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) ->
|
|
[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) ->
|
|
[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) ->
|
|
[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) ->
|
|
[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) ->
|
|
[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) ->
|
|
[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) ->
|
|
[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) ->
|
|
[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) ->
|
|
[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) ->
|
|
[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) ->
|
|
[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) ->
|
|
[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) ->
|
|
[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) ->
|
|
[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) ->
|
|
[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) ->
|
|
[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) ->
|
|
[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) ->
|
|
[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) ->
|
|
[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) ->
|
|
[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) ->
|
|
[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) ->
|
|
[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) ->
|
|
[ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) ->
|
|
[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) ->
|
|
[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) ->
|
|
[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) ->
|
|
[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) ->
|
|
[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) ->
|
|
[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) ->
|
|
[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) ->
|
|
[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) ->
|
|
[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) ->
|
|
[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) ->
|
|
[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) ->
|
|
[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) ->
|
|
[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) ->
|
|
[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) ->
|
|
[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) ->
|
|
[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) ->
|
|
[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) ->
|
|
[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) ->
|
|
[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) ->
|
|
[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) ->
|
|
[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) ->
|
|
[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) ->
|
|
[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) ->
|
|
[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) ->
|
|
[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) ->
|
|
[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) ->
|
|
[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) ->
|
|
[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) ->
|
|
[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) ->
|
|
[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) ->
|
|
[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) ->
|
|
[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) ->
|
|
[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) ->
|
|
[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) ->
|
|
[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) ->
|
|
[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) ->
|
|
[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) ->
|
|
[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) ->
|
|
[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) ->
|
|
[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) ->
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|
[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) ->
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|
[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) ->
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|
[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) ->
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|
[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) ->
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|
[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) ->
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|
[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) ->
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|
[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) ->
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|
[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) ->
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|
[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) ->
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|
[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) ->
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|
[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) ->
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|
[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) ->
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|
[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) ->
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|
[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) ->
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|
[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) ->
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|
[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) ->
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|
[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) ->
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|
[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) ->
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|
[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) ->
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|
[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) ->
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|
[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) ->
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|
[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) ->
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|
[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) ->
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|
[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) ->
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|
[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) ->
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|
[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) ->
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|
[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) ->
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|
[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) ->
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|
[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) ->
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|
[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) ->
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|
[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) ->
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|
[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) ->
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|
[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) ->
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|
[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) ->
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|
[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) ->
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|
[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) ->
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|
[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) ->
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|
[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) ->
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|
[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) ->
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|
[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) ->
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|
[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) ->
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|
[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) ->
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|
[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) ->
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|
[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 232) ->
|
|
[10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) ->
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|
[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) ->
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|
[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) ->
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|
[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) ->
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|
[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) ->
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|
[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) ->
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|
[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) ->
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|
[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) ->
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|
[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) ->
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|
[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) ->
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|
[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) ->
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|
[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) ->
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|
[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) ->
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|
[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) ->
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|
[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) ->
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|
[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) ->
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|
[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) ->
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|
[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) ->
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|
[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) ->
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|
[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) ->
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|
[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) ->
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|
[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) ->
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|
[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) ->
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|
[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) ->
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|
[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) ->
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|
[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) ->
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|
[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) ->
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|
[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) ->
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|
[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) ->
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|
[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) ->
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|
[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) ->
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|
[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) ->
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|
[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) ->
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|
[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) ->
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|
[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) ->
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|
[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) ->
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|
[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) ->
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|
[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) ->
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|
[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) ->
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|
[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) ->
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|
[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) ->
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|
[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) ->
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|
[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) ->
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|
[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) ->
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|
[ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) ->
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|
[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
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|
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
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|
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
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|
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
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|
[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
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|
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
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|
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
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|
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
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|
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
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|
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
|
|
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
|
|
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
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|
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
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|
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
|
|
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
|
|
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
|
|
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
|
|
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
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|
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
|
|
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
|
|
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
|
|
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
|
|
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
|
|
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) ->
|
|
[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) ->
|
|
[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) ->
|
|
[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) ->
|
|
[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) ->
|
|
[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) ->
|
|
[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) ->
|
|
[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) ->
|
|
[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) ->
|
|
[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) ->
|
|
[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) ->
|
|
[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) ->
|
|
[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) ->
|
|
[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) ->
|
|
[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) ->
|
|
[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) ->
|
|
[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) ->
|
|
[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) ->
|
|
[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) ->
|
|
[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) ->
|
|
[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) ->
|
|
[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) ->
|
|
[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) ->
|
|
[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) ->
|
|
[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) ->
|
|
[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) ->
|
|
[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) ->
|
|
[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) ->
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) ->
|
|
[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) ->
|
|
[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) ->
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|
[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) ->
|
|
[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) ->
|
|
[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) ->
|
|
[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) ->
|
|
[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) ->
|
|
[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) ->
|
|
[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) ->
|
|
[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) ->
|
|
[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) ->
|
|
[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) ->
|
|
[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) ->
|
|
[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) ->
|
|
[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) ->
|
|
[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) ->
|
|
[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) ->
|
|
[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) ->
|
|
[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) ->
|
|
[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) ->
|
|
[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) ->
|
|
[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) ->
|
|
[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) ->
|
|
[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) ->
|
|
[ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) ->
|
|
[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) ->
|
|
[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) ->
|
|
[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) ->
|
|
[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) ->
|
|
[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) ->
|
|
[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) ->
|
|
[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) ->
|
|
[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) ->
|
|
[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) ->
|
|
[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) ->
|
|
[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) ->
|
|
[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) ->
|
|
[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) ->
|
|
[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) ->
|
|
[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) ->
|
|
[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) ->
|
|
[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) ->
|
|
[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) ->
|
|
[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) ->
|
|
[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) ->
|
|
[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) ->
|
|
[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) ->
|
|
[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) ->
|
|
[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) ->
|
|
[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) ->
|
|
[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) ->
|
|
[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) ->
|
|
[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) ->
|
|
[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) ->
|
|
[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) ->
|
|
[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) ->
|
|
[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) ->
|
|
[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) ->
|
|
[10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) ->
|
|
[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 304) ->
|
|
[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) ->
|
|
[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) ->
|
|
[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) ->
|
|
[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) ->
|
|
[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) ->
|
|
[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) ->
|
|
[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) ->
|
|
[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) ->
|
|
[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) ->
|
|
[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) ->
|
|
[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) ->
|
|
[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) ->
|
|
[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) ->
|
|
[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) ->
|
|
[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) ->
|
|
[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) ->
|
|
[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) ->
|
|
[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) ->
|
|
[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) ->
|
|
[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) ->
|
|
[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) ->
|
|
[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) ->
|
|
[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) ->
|
|
[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) ->
|
|
[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) ->
|
|
[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) ->
|
|
[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) ->
|
|
[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) ->
|
|
[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) ->
|
|
[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) ->
|
|
[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) ->
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|
[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) ->
|
|
[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) ->
|
|
[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) ->
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|
[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) ->
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|
[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) ->
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|
[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) ->
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|
[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) ->
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|
[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) ->
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|
[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) ->
|
|
[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) ->
|
|
[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) ->
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|
[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) ->
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|
[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) ->
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|
[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) ->
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|
[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) ->
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|
[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) ->
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|
[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) ->
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|
[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) ->
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|
[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) ->
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|
[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) ->
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|
[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) ->
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|
[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) ->
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|
[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) ->
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|
[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) ->
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|
[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) ->
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|
[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) ->
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|
[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) ->
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|
[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) ->
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|
[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) ->
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|
[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) ->
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|
[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) ->
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|
[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) ->
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|
[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) ->
|
|
[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) ->
|
|
[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) ->
|
|
[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) ->
|
|
[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) ->
|
|
[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) ->
|
|
[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) ->
|
|
[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) ->
|
|
[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) ->
|
|
[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) ->
|
|
[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) ->
|
|
[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) ->
|
|
[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) ->
|
|
[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) ->
|
|
[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) ->
|
|
[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) ->
|
|
[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) ->
|
|
[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) ->
|
|
[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) ->
|
|
[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) ->
|
|
[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) ->
|
|
[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) ->
|
|
[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) ->
|
|
[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) ->
|
|
[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) ->
|
|
[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) ->
|
|
[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) ->
|
|
[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) ->
|
|
[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) ->
|
|
[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) ->
|
|
[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) ->
|
|
[ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) ->
|
|
[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) ->
|
|
[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) ->
|
|
[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) ->
|
|
[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) ->
|
|
[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) ->
|
|
[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) ->
|
|
[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) ->
|
|
[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) ->
|
|
[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) ->
|
|
[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) ->
|
|
[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) ->
|
|
[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) ->
|
|
[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) ->
|
|
[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) ->
|
|
[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) ->
|
|
[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) ->
|
|
[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) ->
|
|
[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) ->
|
|
[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) ->
|
|
[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) ->
|
|
[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) ->
|
|
[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) ->
|
|
[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) ->
|
|
[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) ->
|
|
[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) ->
|
|
[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) ->
|
|
[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
|
|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
|
|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: LAST ROW
|
|
Number of Operations: 2304
|
|
Time Started: 148620 ns
|
|
Time Done: 173190 ns
|
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Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
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[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) ->
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|
FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 173270000.0 ps
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[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) ->
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|
[10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) ->
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|
[17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) ->
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|
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) ->
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|
[10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10602) -> [10000 ps] ACT @ (0, 11682) ->
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|
[17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) ->
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|
[17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) ->
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|
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) -> [17500 ps] WR @ (0, 944) -> [ 2500 ps] ACT @ (4, 5206) ->
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|
[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) ->
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|
[17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) ->
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|
[17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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|
[ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) ->
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|
[17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) ->
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|
[17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) ->
|
|
[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) ->
|
|
[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) ->
|
|
[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) ->
|
|
[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) ->
|
|
[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) ->
|
|
[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) ->
|
|
[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) ->
|
|
[10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) ->
|
|
[17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) ->
|
|
[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) ->
|
|
[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) ->
|
|
[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) ->
|
|
[10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) ->
|
|
[17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) ->
|
|
[10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) ->
|
|
[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) ->
|
|
[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) ->
|
|
[10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) ->
|
|
[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) ->
|
|
[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) ->
|
|
[10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) ->
|
|
[17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) ->
|
|
[17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) ->
|
|
[10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) ->
|
|
[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) ->
|
|
[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) ->
|
|
[10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) ->
|
|
[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) ->
|
|
[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) ->
|
|
[10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) ->
|
|
[17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) ->
|
|
[17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9324) ->
|
|
[10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [65000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> [ 2500 ps] ACT @ (4, 3928) ->
|
|
[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) ->
|
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) ->
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[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) ->
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[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) ->
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[10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) ->
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[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) ->
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[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) ->
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[10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) ->
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[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) ->
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[17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) ->
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[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) ->
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[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) ->
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[10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) ->
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[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) ->
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[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) ->
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[17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) ->
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[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) ->
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[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) ->
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[10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) ->
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[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) ->
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[10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) ->
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[17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) ->
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[10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) ->
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[17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) ->
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[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) ->
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[10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) ->
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[17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) ->
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[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) ->
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[10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) ->
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[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) ->
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[17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) ->
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[10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) ->
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[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) ->
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[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) ->
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[10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) ->
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[17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) ->
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[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) ->
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[10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) ->
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[17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) ->
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[17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) ->
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[10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [65000 ps] PRE @ (0) ->
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[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> [ 2500 ps] ACT @ (4, 2650) ->
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[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) ->
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[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) ->
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[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) ->
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[10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) ->
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[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) ->
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[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) ->
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[10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) ->
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[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) ->
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[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) ->
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[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) ->
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[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) ->
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[10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) ->
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[17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) ->
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[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) ->
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[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) ->
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[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) ->
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[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) ->
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[10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) ->
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[17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) ->
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[10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) ->
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[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) ->
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[10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) ->
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[17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) ->
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[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) ->
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[10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) ->
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[17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) ->
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[17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) ->
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[10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) ->
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[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) ->
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[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) ->
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[10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) ->
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[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) ->
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[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) ->
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[10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) ->
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[17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) ->
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[17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) ->
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[10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) ->
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[17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) ->
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[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) ->
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[10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> [65000 ps] PRE @ (0) ->
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[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 7500 ps] WR @ (0, 464) ->
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[10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) ->
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[10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) ->
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[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) ->
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[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) ->
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[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) ->
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[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) ->
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[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) ->
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[17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) ->
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[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) ->
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[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) ->
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[10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) ->
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[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) ->
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[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) ->
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[17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) ->
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[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) ->
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[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) ->
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[10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) ->
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[17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) ->
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[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) ->
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[10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) ->
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[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) ->
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[17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) ->
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[10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) ->
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[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) ->
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[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) ->
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[10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) ->
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[17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) ->
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[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) ->
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[10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) ->
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[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) ->
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[17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) ->
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[10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) ->
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[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) ->
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[17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) ->
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[10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) ->
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[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) ->
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[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> [10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) ->
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[10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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[360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 15399) -> [42500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) ->
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[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) ->
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[17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) ->
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[10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) ->
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[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) ->
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[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) ->
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[10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) ->
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[17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) ->
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[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) ->
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[10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) ->
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[10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) ->
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[10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) ->
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[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) ->
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[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) ->
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[10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) ->
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[10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) ->
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[10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) ->
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[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) ->
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[10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) ->
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[17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) ->
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[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) ->
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[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) ->
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[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) ->
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[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) ->
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[10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) ->
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[17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) ->
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[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) ->
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[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) ->
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[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) ->
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[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) ->
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[10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) ->
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[17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) ->
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[17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) ->
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[10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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[360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [ 2500 ps] ACT @ (0, 14121) -> [42500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) ->
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[10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) ->
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[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) ->
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[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) ->
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[10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) ->
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[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) ->
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[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) ->
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[10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) ->
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[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) ->
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[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) ->
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[17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) ->
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[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) ->
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[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) ->
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[10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) ->
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[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) ->
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[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) ->
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[17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) ->
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[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) ->
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[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) ->
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[10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) ->
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[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) ->
|
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[10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) ->
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[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) ->
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[17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) ->
|
|
[10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) ->
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[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) ->
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[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) ->
|
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[10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) ->
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[17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) ->
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[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) ->
|
|
[ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) ->
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[ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) ->
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[ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 7500 ps] WR @ (7, 1008) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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[360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) -> [10000 ps] ACT @ (0, 16081) -> [ 7500 ps] WR @ (3, 1008) ->
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|
[ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) ->
|
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[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) ->
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[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) ->
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[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) ->
|
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[17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) ->
|
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[10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) ->
|
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[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) ->
|
|
[10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) ->
|
|
[10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) ->
|
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[17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) ->
|
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[10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) ->
|
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[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) ->
|
|
[10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) ->
|
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[10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) ->
|
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[17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) ->
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[10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) ->
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[10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) ->
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[10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) ->
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[10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) ->
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[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) ->
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[10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) ->
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[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) ->
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[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) ->
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[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) ->
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[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) ->
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[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) ->
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[10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) ->
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[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) ->
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[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) ->
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[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) ->
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[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) ->
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[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) ->
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[10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) ->
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[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) ->
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[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) ->
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[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) ->
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[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) ->
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[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) ->
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[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) ->
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[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) ->
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[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) ->
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[10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) ->
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[17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) ->
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|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) ->
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[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) ->
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[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) ->
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|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) ->
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[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) ->
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[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) ->
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[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) ->
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[10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) ->
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[17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) ->
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[10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) ->
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[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) ->
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[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) ->
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[10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) ->
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[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) ->
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[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) ->
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[10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) ->
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[17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) ->
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[17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) ->
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[10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) ->
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[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) ->
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[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) ->
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[10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) ->
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[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) ->
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[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) ->
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[10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) ->
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[17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) ->
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[17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) ->
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[10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [ 5000 ps] NOP ->
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[40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) ->
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[17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 3814) ->
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[17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) ->
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[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) ->
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[10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) ->
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[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) ->
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[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) ->
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[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) ->
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[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) ->
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[10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) ->
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[17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) ->
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[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) ->
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[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) ->
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[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) ->
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[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) ->
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[10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) ->
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[17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) ->
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[10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) ->
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[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) ->
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[10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) ->
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[17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) ->
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[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) ->
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[10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) ->
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[17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) ->
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[17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) ->
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[10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) ->
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[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) ->
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[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) ->
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[10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) ->
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[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) ->
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[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) ->
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[10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) ->
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[17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) ->
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[17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) ->
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[10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) ->
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[17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) ->
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[17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) ->
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[10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) ->
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[15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) ->
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[10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) ->
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[ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) ->
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[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) ->
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[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) ->
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[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) ->
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[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) ->
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[10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) ->
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[ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) ->
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[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) ->
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[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) ->
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[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) ->
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[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) ->
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[10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) ->
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[15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) ->
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[15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) ->
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[10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) ->
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[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) ->
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[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) ->
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[10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) ->
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[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) ->
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[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) ->
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[10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) ->
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[15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) ->
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[15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) ->
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[10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) ->
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[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) ->
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[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) ->
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[10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) ->
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[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) ->
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[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) ->
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[10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> [67500 ps] PRE @ (0) ->
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[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) ->
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|
[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 840) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> [ 5000 ps] RD @ (4, 840) ->
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[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) ->
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[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> [10000 ps] RD @ (4, 832) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> [ 5000 ps] RD @ (4, 832) ->
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[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) ->
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[10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) ->
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[15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [15000 ps] RD @ (4, 816) ->
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[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> [10000 ps] ACT @ (4, 3536) ->
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[ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [15000 ps] RD @ (4, 816) ->
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[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) ->
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[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [15000 ps] RD @ (4, 808) ->
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[10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> [10000 ps] ACT @ (4, 9128) ->
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[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [15000 ps] RD @ (4, 800) ->
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[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) ->
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[ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [15000 ps] RD @ (4, 800) ->
|
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[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> [10000 ps] ACT @ (4, 14720) ->
|
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[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) ->
|
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [15000 ps] RD @ (4, 792) ->
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[10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) ->
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[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) ->
|
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[10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) ->
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[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) ->
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[15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2849) ->
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[10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) ->
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[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) ->
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[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) ->
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[10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) ->
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[15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) ->
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[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8441) ->
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[10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) ->
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[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) ->
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[15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) ->
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[10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) ->
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[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) ->
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[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14033) ->
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[10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) ->
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[15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) ->
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[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) ->
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[10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) ->
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[10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) ->
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[10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) ->
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[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) ->
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[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) ->
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[10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) ->
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[10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) ->
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[10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) ->
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[15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) ->
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[10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) ->
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[ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) ->
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[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) ->
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[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) ->
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[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) ->
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[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) ->
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[10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) ->
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[ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) ->
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[10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) ->
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[ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) ->
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[15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [67500 ps] PRE @ (0) ->
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[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) -> [15000 ps] RD @ (4, 624) -> [ 5000 ps] ACT @ (0, 492) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) ->
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[10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) ->
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[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) ->
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[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) ->
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[10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) ->
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[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) ->
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[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) ->
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[10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) ->
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[15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) ->
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[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) ->
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[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) ->
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[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) ->
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[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) ->
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[10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) ->
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[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) ->
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[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) ->
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[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) ->
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[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) ->
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[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) ->
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[10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) ->
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[ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) ->
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[10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) ->
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[15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) ->
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[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) ->
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[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) ->
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[15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) ->
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[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) ->
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[10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) ->
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[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) ->
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[15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) ->
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[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) ->
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[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) ->
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[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) ->
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[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) ->
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[15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) ->
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[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) ->
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[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) ->
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[15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) ->
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[15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) ->
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[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) ->
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[10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) ->
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[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> [10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) ->
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[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) ->
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[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) ->
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[ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) ->
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[10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) ->
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[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) ->
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[10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) ->
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[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) ->
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[10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) ->
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[ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) ->
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[10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) ->
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[15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) ->
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[15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) ->
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[10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) ->
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[15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) ->
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[15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) ->
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[10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) ->
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[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) ->
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[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3627) ->
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[10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) ->
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[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) ->
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[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) ->
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[10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) ->
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[15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) ->
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[15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9219) ->
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[10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) ->
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[15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) ->
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[15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) ->
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[10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 304) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 296) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> [10000 ps] RD @ (0, 296) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 288) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 280) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [15000 ps] RD @ (0, 280) ->
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[10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> [10000 ps] RD @ (0, 280) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> [ 5000 ps] RD @ (0, 280) ->
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[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 272) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> [ 5000 ps] RD @ (0, 272) ->
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[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 264) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> [ 5000 ps] RD @ (0, 264) ->
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[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> [10000 ps] RD @ (0, 264) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> [ 5000 ps] RD @ (0, 264) ->
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[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 256) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> [ 5000 ps] RD @ (0, 256) ->
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[10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 248) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> [ 5000 ps] RD @ (0, 248) ->
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[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) ->
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[15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [15000 ps] RD @ (0, 248) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) ->
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[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> [10000 ps] ACT @ (0, 6274) ->
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[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [15000 ps] RD @ (0, 240) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [15000 ps] RD @ (0, 240) ->
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[10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> [10000 ps] ACT @ (0, 878) ->
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[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [15000 ps] RD @ (0, 232) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) ->
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[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> [10000 ps] ACT @ (0, 11866) ->
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[ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [15000 ps] RD @ (0, 232) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [15000 ps] RD @ (0, 232) ->
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[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> [10000 ps] ACT @ (0, 6470) ->
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[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [15000 ps] RD @ (0, 224) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) ->
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[10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> [10000 ps] ACT @ (0, 1074) ->
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[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [15000 ps] RD @ (0, 216) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [15000 ps] RD @ (0, 216) ->
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[10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> [10000 ps] ACT @ (0, 12062) ->
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[ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) ->
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[10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) ->
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[15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) ->
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[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5587) ->
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[10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) ->
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[15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) ->
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[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 191) ->
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[10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) ->
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[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) ->
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[15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11179) ->
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[10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) ->
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[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) ->
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[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5783) ->
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[10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) ->
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[15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) ->
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[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 387) ->
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[10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) ->
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[15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) ->
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[15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) ->
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[10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (4, 184) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) ->
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[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) ->
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[ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) ->
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[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) ->
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[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) ->
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[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) ->
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[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) ->
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[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) ->
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[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) ->
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[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) ->
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[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) ->
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[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) ->
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[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) ->
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[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) ->
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[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) ->
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[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) ->
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[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) ->
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[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) ->
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[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) ->
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[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) ->
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[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) ->
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[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) ->
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[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) ->
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[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) ->
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[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) ->
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[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) ->
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[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) ->
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[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) ->
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[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) ->
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[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) ->
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[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) ->
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[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) ->
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[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) ->
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[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) ->
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[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) ->
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[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) ->
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[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) ->
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[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) ->
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[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) ->
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[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) ->
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[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) ->
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[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) ->
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[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) ->
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[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) ->
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[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) ->
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[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) ->
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[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) ->
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[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) ->
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[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) ->
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[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) ->
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[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) ->
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[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) ->
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[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) ->
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[10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) ->
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[10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7447) ->
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[10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) ->
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[10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) ->
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[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 3130) -> [10000 ps] ACT @ (3, 3130) ->
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[15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) ->
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[15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) ->
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[ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> [ 5000 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) ->
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[10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) ->
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[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) ->
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[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) ->
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[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) ->
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[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) ->
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[10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) ->
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[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) ->
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[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) ->
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[10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) ->
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[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) ->
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[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) ->
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[10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) ->
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[15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) ->
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[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) ->
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[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) ->
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[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) ->
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[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) ->
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[10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) ->
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[ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) ->
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[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) ->
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[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) ->
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[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) ->
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[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) ->
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[10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) ->
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[ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) ->
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[10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) ->
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[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) ->
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[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) ->
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[10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) ->
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[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) ->
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[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) ->
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[10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) ->
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[15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) ->
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[15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) ->
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[10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) ->
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[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) ->
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[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) ->
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[10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) ->
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[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) ->
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[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) ->
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[10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) ->
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[15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) ->
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[15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) ->
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[10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) ->
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[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) ->
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[10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) ->
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[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) ->
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[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) ->
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[10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) ->
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[10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) ->
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[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) ->
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[ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) ->
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--------------------------------
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DONE TEST 2: RANDOM
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Number of Operations: 2304
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Time Started: 173290 ns
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Time Done: 282900 ns
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Average Rate: 47 ns/request
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--------------------------------
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[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) ->
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[10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 283030000.0 ps
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------- SUMMARY -------
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Number of Writes = 4608
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Number of Reads = 4608
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Number of Success = 4604
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Number of Fails = 4
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Number of Injected Errors = 4
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$stop called at time : 284 us : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
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run: Time (s): cpu = 00:00:17 ; elapsed = 00:53:20 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1238 ; free virtual = 24677
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## quit
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INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3147150 ms
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INFO: [Common 17-206] Exiting xsim at Wed Jul 5 16:43:17 2023...
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