14162 lines
2.2 MiB
14162 lines
2.2 MiB
#-----------------------------------------------------------
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# xsim v2021.2 (64-bit)
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# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
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# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
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# Start of session at: Wed Jul 5 15:01:38 2023
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# Process ID: 10611
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# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
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# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
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# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
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# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
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# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3667.243 MHz, CPU Physical cores: 2, Host memory: 7450 MB
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#-----------------------------------------------------------
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source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
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# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
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Time resolution is 1 ps
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source cmd.tcl
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## set curr_wave [current_wave_config]
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## if { [string length $curr_wave] == 0 } {
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## if { [llength [get_objects]] > 0} {
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## add_wave /
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## set_property needs_save false [current_wave_config]
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## } else {
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## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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## }
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## }
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## run -all
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Test ns_to_cycles() function:
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ns_to_cycles(15) = 3 = 2 [exact]
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ns_to_cycles(14.5) = 3 = 2 [round-off]
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ns_to_cycles(11) = 3 = 2 [round-up]
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Test nCK_to_cycles() function:
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ns_to_cycles(16) = 4 = 4 [exact]
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ns_to_cycles(15) = 4 = 4 [round-off]
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ns_to_cycles(13) = 4 = 4 [round-up]
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Test ns_to_nCK() function:
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ns_to_cycles(15) = 12 = 6 [exact]
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ns_to_cycles(14.875) = 12 = 6 [round-off]
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ns_to_cycles(13.875) = 12 = 6 [round-up]
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ns_to_nCK(tRCD) = 11 = 6 [WRONG]
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tRTP = 7.5 = 10.000000
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ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test $floor() function:
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$floor(5/2) = 2.5 = 2
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$floor(9/4) = 2.25 = 2
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$floor(9/4) = 2 = 2
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$floor(9/5) = 1.8 = 1
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DELAY_COUNTER_WIDTH = 16
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DELAY_SLOT_WIDTH = 19
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serdes_ratio = 4
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wb_addr_bits = 24
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wb_data_bits = 512
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wb_sel_bits = 64
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READ_SLOT = 2
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WRITE_SLOT = 3
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ACTIVATE_SLOT = 0
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PRECHARGE_SLOT = 1
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DELAYS:
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ns_to_nCK(tRCD): 6
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ns_to_nCK(tRP): 6
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ns_to_nCK(tRTP): 4
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tCCD: 4
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(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
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(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
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(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
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$signed(4'b1100)>>>4: 1111
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PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
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ACTIVATE_TO_WRITE_DELAY = 3 = 0
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ACTIVATE_TO_READ_DELAY = 2 = 0
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READ_TO_WRITE_DELAY = 2 = 1
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READ_TO_READ_DELAY = 0 = 0
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READ_TO_PRECHARGE_DELAY = 1 =1
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WRITE_TO_WRITE_DELAY = 0 = 0
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WRITE_TO_READ_DELAY = 4 = 3
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WRITE_TO_PRECHARGE_DELAY = 5 = 4
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STAGE2_DATA_DEPTH = 2 = 2
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READ_ACK_PIPE_WIDTH = 6
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ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive.
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[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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[510000 ps] NOP -> [370000 ps] MRS ->
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ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
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[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [247500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP ->
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[110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27472027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27474527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27477027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27479527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27482027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27484527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27487027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27489527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27492027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27494527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27622105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27624605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27627105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27629605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27632105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27634605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27637105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27639605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27642105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27644605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29573225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29575725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29578225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29580725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29583225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29585725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29588225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29590725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29593225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29595725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29723225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29725725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29728225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29730725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29733225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29735725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29738225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29740725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29743225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29745725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30322027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30324527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30327027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30329527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30332027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30334527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30337027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30339527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30342027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30344527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30472105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30474605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30477105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30479605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30482105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30484605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30487105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30489605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30492105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30494605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32423225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32425725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32428225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32430725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32433225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32435725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32438225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32440725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32443225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32445725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32573225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32575725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32578225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32580725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32583225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32585725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32588225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32590725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32593225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32595725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33172027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33174527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33177027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33179527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33182027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33184527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33187027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33189527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33192027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33194527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33322105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33324605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33327105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33329605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33332105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33334605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33337105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33339605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33342105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33344605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35273225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35275725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35278225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35280725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35283225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35285725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35288225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35290725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35293225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35295725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35423225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35425725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35428225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35430725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35433225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35435725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35438225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35440725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35443225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35445725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36022027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36024527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36027027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36029527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36032027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36034527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36037027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36039527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36042027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36044527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36172105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36174605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36177105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36179605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36182105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36184605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36187105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36189605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36192105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36194605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38123225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38125725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38128225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38130725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38133225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38135725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38138225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38140725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38143225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38145725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38273225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38275725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38278225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38280725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38283225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38285725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38288225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38290725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38293225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38295725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38872027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38874527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38877027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38879527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38882027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38884527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38887027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38889527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38892027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38894527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39022105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39024605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39027105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39029605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39032105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39034605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39037105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39039605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39042105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39044605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40973225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40975725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40978225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40980725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40983225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40985725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40988225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40990725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40993225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40995725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41123225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41125725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41128225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41130725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41133225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41135725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41138225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41140725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41143225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41145725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41722027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41724527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41727027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41729527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41732027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41734527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41737027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41739527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41742027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41744527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41872105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41874605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41877105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41879605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41882105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41884605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41887105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41889605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41892105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41894605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43823225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43825725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43828225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43830725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43833225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43835725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43838225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43840725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43843225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43845725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43973225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43975725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43978225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43980725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43983225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43985725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43988225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43990725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43993225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43995725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44572027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44574527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44577027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44579527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44582027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44584527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44587027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44589527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44592027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44594527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44722105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44724605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44727105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44729605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44732105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44734605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44737105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44739605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44742105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44744605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46673225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46675725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46678225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46680725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46683225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46685725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46688225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46690725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46693225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46695725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46823225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46825725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46828225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46830725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46833225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46835725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46838225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46840725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46843225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46845725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47422027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47424527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47427027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47429527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47432027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47434527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47437027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47439527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47442027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47444527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47572105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47574605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47577105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47579605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47582105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47584605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47587105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47589605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47592105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47594605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49523225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49525725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49528225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49530725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49533225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49535725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49538225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49540725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49543225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49545725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49673225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49675725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49678225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49680725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49683225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49685725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49688225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49690725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49693225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49695725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
[22670000 ps] MRS -> [10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF ->
|
|
[360000 ps] NOP -> [37500 ps] ACT @ (0, 0) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) ->
|
|
[202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
|
|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
|
|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
|
|
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
|
|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
|
|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
|
|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
|
|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
|
|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
|
|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
|
|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
|
|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
|
|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
|
|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
|
|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
|
|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
|
|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
|
|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) ->
|
|
[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) ->
|
|
[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) ->
|
|
[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) ->
|
|
[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) ->
|
|
[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) ->
|
|
[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) ->
|
|
[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) ->
|
|
[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) ->
|
|
[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) ->
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|
[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) ->
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[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) ->
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[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) ->
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|
[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) ->
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[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) ->
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|
[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) ->
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|
[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) ->
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|
[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) ->
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|
[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) ->
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|
[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) ->
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|
[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) ->
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|
[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) ->
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|
[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) ->
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|
[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) ->
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|
[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) ->
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|
[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) ->
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|
[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) ->
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|
[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) ->
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|
[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) ->
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|
[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) ->
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|
[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) ->
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|
[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) ->
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|
[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) ->
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|
[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) ->
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|
[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) ->
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|
[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) ->
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|
[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) ->
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|
[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) ->
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|
[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) ->
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|
[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) ->
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|
[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) ->
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|
[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) ->
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|
[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) ->
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|
[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) ->
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|
[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) ->
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|
[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) ->
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|
[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) ->
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|
[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) ->
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|
[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) ->
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|
[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) ->
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|
[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) ->
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|
[ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) ->
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|
[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) ->
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|
[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) ->
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|
[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) ->
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|
[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) ->
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|
[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) ->
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|
[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) ->
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|
[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) ->
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|
[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) ->
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|
[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) ->
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|
[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) ->
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|
[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) ->
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|
[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) ->
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|
[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) ->
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|
[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) ->
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|
[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) ->
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|
[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) ->
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|
[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) ->
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|
[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) ->
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|
[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) ->
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|
[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) ->
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|
[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) ->
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|
[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) ->
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|
[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) ->
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|
[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) ->
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|
[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) ->
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|
[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) ->
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|
[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) ->
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|
[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) ->
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|
[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) ->
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|
[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) ->
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|
[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) ->
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|
[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) ->
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|
[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) ->
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|
[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) ->
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|
[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) ->
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|
[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) ->
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|
[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) ->
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|
[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) ->
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|
[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) ->
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|
[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) ->
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|
[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) ->
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|
[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) ->
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|
[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) ->
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|
[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) ->
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|
[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) ->
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|
[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) ->
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|
[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) ->
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|
[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) ->
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|
[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) ->
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|
[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) ->
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|
[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) ->
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|
[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) ->
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|
[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) ->
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|
[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) ->
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|
[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) ->
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|
[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) ->
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|
[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) ->
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|
[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) ->
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|
[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) ->
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|
[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) ->
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|
[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) ->
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|
[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) ->
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|
[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) ->
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|
[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) ->
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|
[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) ->
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|
[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) ->
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|
[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) ->
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|
[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) ->
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|
[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) ->
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|
[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) ->
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|
[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) ->
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|
[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) ->
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|
[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) ->
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|
[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) ->
|
|
[10000 ps] WR @ (5, 880) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) ->
|
|
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) ->
|
|
[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) ->
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|
[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) ->
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|
[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) ->
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|
[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) ->
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|
[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) ->
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|
[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) ->
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|
[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) ->
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|
[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) ->
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|
[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) ->
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|
[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) ->
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|
[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) ->
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|
[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) ->
|
|
[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) ->
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|
[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) ->
|
|
[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) ->
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|
[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) ->
|
|
[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) ->
|
|
[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) ->
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|
[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) ->
|
|
[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) ->
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|
[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) ->
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|
[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) ->
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|
[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) ->
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|
[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) ->
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|
[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) ->
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|
[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) ->
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|
[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) ->
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|
[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) ->
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|
[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) ->
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|
[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) ->
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|
[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) ->
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|
[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) ->
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|
[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) ->
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|
[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) ->
|
|
[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) ->
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|
[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) ->
|
|
[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) ->
|
|
[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) ->
|
|
[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) ->
|
|
[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) ->
|
|
[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) ->
|
|
[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) ->
|
|
[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) ->
|
|
[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) ->
|
|
[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) ->
|
|
[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) ->
|
|
[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) ->
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|
[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) ->
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|
[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) ->
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|
[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) ->
|
|
[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) ->
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|
[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) ->
|
|
[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) ->
|
|
[ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) ->
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|
[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
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|
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
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|
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
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|
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
|
|
[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
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|
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
|
|
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
|
|
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
|
|
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
|
|
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
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|
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
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|
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
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|
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
|
|
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
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|
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
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|
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
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|
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
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|
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
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|
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
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|
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
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|
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
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|
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
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|
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
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|
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
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|
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) ->
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|
[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) ->
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|
[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) ->
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|
[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) ->
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|
[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) ->
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|
[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) ->
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|
[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) ->
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|
[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) ->
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|
[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) ->
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|
[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) ->
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|
[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) ->
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|
[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) ->
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|
[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) ->
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|
[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) ->
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|
[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) ->
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|
[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) ->
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|
[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) ->
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|
[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) ->
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|
[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) ->
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|
[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) ->
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|
[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) ->
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|
[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) ->
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|
[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) ->
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|
[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) ->
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|
[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) ->
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|
[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) ->
|
|
[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) ->
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|
[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) ->
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|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) ->
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|
[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) ->
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|
[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) ->
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|
[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) ->
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|
[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) ->
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|
[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) ->
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|
[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) ->
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|
[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) ->
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|
[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) ->
|
|
[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) ->
|
|
[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) ->
|
|
[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) ->
|
|
[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) ->
|
|
[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) ->
|
|
[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) ->
|
|
[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) ->
|
|
[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) ->
|
|
[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) ->
|
|
[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) ->
|
|
[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) ->
|
|
[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) ->
|
|
[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) ->
|
|
[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) ->
|
|
[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) ->
|
|
[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) ->
|
|
[ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) ->
|
|
[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) ->
|
|
[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) ->
|
|
[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) ->
|
|
[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) ->
|
|
[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) ->
|
|
[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) ->
|
|
[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) ->
|
|
[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) ->
|
|
[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) ->
|
|
[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) ->
|
|
[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) ->
|
|
[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) ->
|
|
[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) ->
|
|
[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) ->
|
|
[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) ->
|
|
[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) ->
|
|
[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) ->
|
|
[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) ->
|
|
[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) ->
|
|
[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) ->
|
|
[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) ->
|
|
[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) ->
|
|
[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) ->
|
|
[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP ->
|
|
[ 2500 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF ->
|
|
[360000 ps] NOP -> [17500 ps] ACT @ (2, 0) -> [15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) ->
|
|
[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) ->
|
|
[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) ->
|
|
[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) ->
|
|
[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) ->
|
|
[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) ->
|
|
[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) ->
|
|
[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) ->
|
|
[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) ->
|
|
[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) ->
|
|
[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) ->
|
|
[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) ->
|
|
[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) ->
|
|
[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) ->
|
|
[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) ->
|
|
[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) ->
|
|
[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) ->
|
|
[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) ->
|
|
[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) ->
|
|
[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) ->
|
|
[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) ->
|
|
[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) ->
|
|
[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) ->
|
|
[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) ->
|
|
[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) ->
|
|
[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) ->
|
|
[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) ->
|
|
[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) ->
|
|
[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) ->
|
|
[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) ->
|
|
[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) ->
|
|
[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) ->
|
|
[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) ->
|
|
[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) ->
|
|
[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) ->
|
|
[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) ->
|
|
[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) ->
|
|
[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) ->
|
|
[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) ->
|
|
[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) ->
|
|
[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) ->
|
|
[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) ->
|
|
[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) ->
|
|
[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) ->
|
|
[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) ->
|
|
[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) ->
|
|
[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) ->
|
|
[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) ->
|
|
[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) ->
|
|
[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) ->
|
|
[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) ->
|
|
[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) ->
|
|
[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) ->
|
|
[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) ->
|
|
[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) ->
|
|
[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) ->
|
|
[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) ->
|
|
[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) ->
|
|
[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) ->
|
|
[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) ->
|
|
[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) ->
|
|
[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) ->
|
|
[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) ->
|
|
[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) ->
|
|
[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) ->
|
|
[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) ->
|
|
[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) ->
|
|
[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) ->
|
|
[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) ->
|
|
[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) ->
|
|
[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) ->
|
|
[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) ->
|
|
[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) ->
|
|
[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) ->
|
|
[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) ->
|
|
[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) ->
|
|
[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) ->
|
|
[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) ->
|
|
[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) ->
|
|
[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) ->
|
|
[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) ->
|
|
[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) ->
|
|
[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) ->
|
|
[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) ->
|
|
[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) ->
|
|
[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) ->
|
|
[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) ->
|
|
[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) ->
|
|
[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) ->
|
|
[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) ->
|
|
[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) ->
|
|
[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) ->
|
|
[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) ->
|
|
[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) ->
|
|
[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) ->
|
|
[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) ->
|
|
[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) ->
|
|
[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) ->
|
|
[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) ->
|
|
[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) ->
|
|
[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) ->
|
|
[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) ->
|
|
[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) ->
|
|
[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) ->
|
|
[ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) ->
|
|
[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) ->
|
|
[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) ->
|
|
[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) ->
|
|
[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) ->
|
|
[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) ->
|
|
[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) ->
|
|
[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) ->
|
|
[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) ->
|
|
[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) ->
|
|
[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) ->
|
|
[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) ->
|
|
[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) ->
|
|
[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) ->
|
|
[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) ->
|
|
[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) ->
|
|
[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) ->
|
|
[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) ->
|
|
[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) ->
|
|
[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) ->
|
|
[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) ->
|
|
[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) ->
|
|
[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) ->
|
|
[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) ->
|
|
[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) ->
|
|
[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) ->
|
|
[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) ->
|
|
[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
|
|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
|
|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: FIRST ROW
|
|
Number of Operations: 2304
|
|
Time Started: 50650 ns
|
|
Time Done: 74740 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) ->
|
|
[27500 ps] NOP -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 74820000.0 ps
|
|
[70000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) ->
|
|
[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
|
|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
|
|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
|
|
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
|
|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
|
|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
|
|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
|
|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
|
|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
|
|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
|
|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
|
|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
|
|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
|
|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
|
|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
|
|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
|
|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
|
|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) ->
|
|
[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) ->
|
|
[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) ->
|
|
[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) ->
|
|
[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) ->
|
|
[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) ->
|
|
[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) ->
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|
[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) ->
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|
[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) ->
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[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) ->
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|
[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) ->
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|
[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) ->
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|
[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) ->
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|
[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) ->
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|
[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) ->
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|
[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) ->
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|
[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) ->
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|
[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) ->
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|
[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) ->
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|
[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) ->
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|
[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) ->
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|
[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) ->
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|
[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) ->
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|
[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) ->
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|
[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) ->
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|
[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) ->
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|
[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) ->
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|
[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) ->
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|
[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) ->
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|
[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) ->
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|
[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) ->
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|
[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) ->
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|
[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) ->
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|
[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) ->
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|
[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) ->
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|
[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) ->
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|
[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) ->
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|
[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) ->
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|
[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) ->
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|
[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) ->
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|
[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) ->
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|
[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) ->
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|
[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) ->
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|
[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) ->
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|
[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) ->
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|
[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) ->
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|
[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) ->
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|
[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) ->
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|
[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) ->
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|
[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) ->
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|
[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) ->
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|
[ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) ->
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|
[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) ->
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|
[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) ->
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|
[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) ->
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|
[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) ->
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|
[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) ->
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|
[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) ->
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|
[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) ->
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|
[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) ->
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|
[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) ->
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|
[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) ->
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|
[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) ->
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|
[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) ->
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|
[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) ->
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|
[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) ->
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|
[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) ->
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|
[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) ->
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|
[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) ->
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|
[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) ->
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|
[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) ->
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|
[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) ->
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|
[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) ->
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|
[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) ->
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|
[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) ->
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|
[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) ->
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|
[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) ->
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|
[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) ->
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|
[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) ->
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|
[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) ->
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|
[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) ->
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|
[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) ->
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|
[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) ->
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|
[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) ->
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|
[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) ->
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|
[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) ->
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|
[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) ->
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|
[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) ->
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|
[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) ->
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|
[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) ->
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|
[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) ->
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|
[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) ->
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|
[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) ->
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|
[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) ->
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|
[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) ->
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|
[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) ->
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|
[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) ->
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|
[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) ->
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|
[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) ->
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|
[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) ->
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|
[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) ->
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|
[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) ->
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|
[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) ->
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|
[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) ->
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|
[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) ->
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|
[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) ->
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|
[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) ->
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|
[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) ->
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|
[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) ->
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|
[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) ->
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|
[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) ->
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|
[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) ->
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|
[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) ->
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|
[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) ->
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|
[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) ->
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|
[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) ->
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|
[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) ->
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|
[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) ->
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|
[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) ->
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|
[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) ->
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|
[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) ->
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|
[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) ->
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|
[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) ->
|
|
[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) ->
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|
[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) ->
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|
[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) ->
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|
[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) ->
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|
[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) ->
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|
[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) ->
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|
[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) ->
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|
[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) ->
|
|
[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) ->
|
|
[10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[17500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) ->
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|
[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) ->
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|
[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) ->
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|
[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) ->
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|
[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) ->
|
|
[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) ->
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|
[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) ->
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|
[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) ->
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|
[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) ->
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|
[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) ->
|
|
[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) ->
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|
[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) ->
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|
[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) ->
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|
[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) ->
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|
[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) ->
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|
[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) ->
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|
[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) ->
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|
[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) ->
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|
[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) ->
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|
[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) ->
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|
[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) ->
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|
[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) ->
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|
[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) ->
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|
[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) ->
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|
[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) ->
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|
[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) ->
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|
[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) ->
|
|
[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) ->
|
|
[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) ->
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|
[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) ->
|
|
[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) ->
|
|
[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) ->
|
|
[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) ->
|
|
[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) ->
|
|
[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) ->
|
|
[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) ->
|
|
[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) ->
|
|
[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) ->
|
|
[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) ->
|
|
[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) ->
|
|
[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) ->
|
|
[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) ->
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|
[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) ->
|
|
[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) ->
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|
[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) ->
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|
[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) ->
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|
[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) ->
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|
[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) ->
|
|
[ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) ->
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|
[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
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|
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
|
|
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
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|
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
|
|
[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
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|
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
|
|
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
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|
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
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|
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
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|
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
|
|
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
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|
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
|
|
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
|
|
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
|
|
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
|
|
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
|
|
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
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|
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
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|
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
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|
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
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|
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
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|
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
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|
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
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|
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
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|
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) ->
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|
[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) ->
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|
[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) ->
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|
[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) ->
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|
[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) ->
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|
[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) ->
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|
[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) ->
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|
[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) ->
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|
[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) ->
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|
[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) ->
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|
[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) ->
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|
[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) ->
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|
[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) ->
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|
[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) ->
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|
[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) ->
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|
[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) ->
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|
[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) ->
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|
[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) ->
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|
[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) ->
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|
[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) ->
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|
[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) ->
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|
[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) ->
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|
[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) ->
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|
[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) ->
|
|
[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) ->
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|
[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) ->
|
|
[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) ->
|
|
[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) ->
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|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) ->
|
|
[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) ->
|
|
[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) ->
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|
[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) ->
|
|
[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) ->
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|
[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) ->
|
|
[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) ->
|
|
[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) ->
|
|
[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) ->
|
|
[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) ->
|
|
[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) ->
|
|
[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) ->
|
|
[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) ->
|
|
[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) ->
|
|
[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) ->
|
|
[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) ->
|
|
[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) ->
|
|
[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) ->
|
|
[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) ->
|
|
[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) ->
|
|
[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) ->
|
|
[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) ->
|
|
[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) ->
|
|
[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) ->
|
|
[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) ->
|
|
[ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) ->
|
|
[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) ->
|
|
[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) ->
|
|
[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) ->
|
|
[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) ->
|
|
[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) ->
|
|
[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) ->
|
|
[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) ->
|
|
[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) ->
|
|
[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) ->
|
|
[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) ->
|
|
[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) ->
|
|
[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) ->
|
|
[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) ->
|
|
[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) ->
|
|
[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) ->
|
|
[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) ->
|
|
[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) ->
|
|
[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) ->
|
|
[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) ->
|
|
[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) ->
|
|
[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) ->
|
|
[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) ->
|
|
[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) ->
|
|
[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) ->
|
|
[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) ->
|
|
[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) ->
|
|
[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) ->
|
|
[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) ->
|
|
[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) ->
|
|
[10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) ->
|
|
[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) ->
|
|
[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) ->
|
|
[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) ->
|
|
[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) ->
|
|
[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) ->
|
|
[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) ->
|
|
[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) ->
|
|
[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) ->
|
|
[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) ->
|
|
[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) ->
|
|
[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) ->
|
|
[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) ->
|
|
[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) ->
|
|
[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) ->
|
|
[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) ->
|
|
[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) ->
|
|
[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) ->
|
|
[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) ->
|
|
[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) ->
|
|
[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) ->
|
|
[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) ->
|
|
[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) ->
|
|
[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) ->
|
|
[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) ->
|
|
[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) ->
|
|
[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) ->
|
|
[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) ->
|
|
[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) ->
|
|
[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) ->
|
|
[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) ->
|
|
[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) ->
|
|
[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) ->
|
|
[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) ->
|
|
[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) ->
|
|
[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) ->
|
|
[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) ->
|
|
[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) ->
|
|
[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) ->
|
|
[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) ->
|
|
[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) ->
|
|
[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) ->
|
|
[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) ->
|
|
[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) ->
|
|
[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) ->
|
|
[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) ->
|
|
[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) ->
|
|
[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) ->
|
|
[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) ->
|
|
[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) ->
|
|
[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) ->
|
|
[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) ->
|
|
[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) ->
|
|
[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) ->
|
|
[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) ->
|
|
[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) ->
|
|
[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) ->
|
|
[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) ->
|
|
[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) ->
|
|
[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) ->
|
|
[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) ->
|
|
[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) ->
|
|
[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) ->
|
|
[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) ->
|
|
[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) ->
|
|
[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) ->
|
|
[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) ->
|
|
[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) ->
|
|
[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) ->
|
|
[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) ->
|
|
[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) ->
|
|
[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) ->
|
|
[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) ->
|
|
[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) ->
|
|
[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) ->
|
|
[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) ->
|
|
[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) ->
|
|
[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) ->
|
|
[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) ->
|
|
[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) ->
|
|
[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) ->
|
|
[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) ->
|
|
[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) ->
|
|
[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) ->
|
|
[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) ->
|
|
[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) ->
|
|
[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) ->
|
|
[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) ->
|
|
[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) ->
|
|
[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) ->
|
|
[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) ->
|
|
[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) ->
|
|
[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) ->
|
|
[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) ->
|
|
[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) ->
|
|
[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) ->
|
|
[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) ->
|
|
[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) ->
|
|
[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) ->
|
|
[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) ->
|
|
[ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) ->
|
|
[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) ->
|
|
[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) ->
|
|
[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) ->
|
|
[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) ->
|
|
[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) ->
|
|
[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) ->
|
|
[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) ->
|
|
[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) ->
|
|
[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) ->
|
|
[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) ->
|
|
[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) ->
|
|
[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) ->
|
|
[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) ->
|
|
[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) ->
|
|
[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) ->
|
|
[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) ->
|
|
[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) ->
|
|
[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) ->
|
|
[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) ->
|
|
[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) ->
|
|
[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) ->
|
|
[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) ->
|
|
[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) ->
|
|
[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) ->
|
|
[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) ->
|
|
[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) ->
|
|
[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
|
|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
|
|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: MIDDLE ROW
|
|
Number of Operations: 2304
|
|
Time Started: 74840 ns
|
|
Time Done: 99330 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) ->
|
|
FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 99410000.0 ps
|
|
[97500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
|
|
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
|
|
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
|
|
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) ->
|
|
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
|
|
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
|
|
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
|
|
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
|
|
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
|
|
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
|
|
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
|
|
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
|
|
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
|
|
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
|
|
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
|
|
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
|
|
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
|
|
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
|
|
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
|
|
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
|
|
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
|
|
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
|
|
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
|
|
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) ->
|
|
[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) ->
|
|
[10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) ->
|
|
[10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) ->
|
|
[10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) ->
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[10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) ->
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[10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) ->
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[10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) ->
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[10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) ->
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[10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) ->
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[10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) ->
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[10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) ->
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[10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) ->
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[10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) ->
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[10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) ->
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[10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) ->
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[10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) ->
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[10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) ->
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[10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) ->
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[10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) ->
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[10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) ->
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[10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) ->
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[10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) ->
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[10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) ->
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[10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) ->
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[10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) ->
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[10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) ->
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|
[10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) ->
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[10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) ->
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[10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) ->
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[10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) ->
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[10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) ->
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[10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) ->
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[10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) ->
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[10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) ->
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[10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) ->
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[10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) ->
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[10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) ->
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[10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) ->
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[10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) ->
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[10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) ->
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[10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) ->
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[10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) ->
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[10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) ->
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[10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) ->
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[10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) ->
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[10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) ->
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[10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) ->
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[10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) ->
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[10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) ->
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[10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) ->
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[10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) ->
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[10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) ->
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[10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) ->
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[10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) ->
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[10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) ->
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[10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) ->
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[10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) ->
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[10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) ->
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[10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) ->
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[10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) ->
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[10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) ->
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[10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) ->
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[10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) ->
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[10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) ->
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[10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) ->
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[10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) ->
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[10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) ->
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|
[10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) ->
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[10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) ->
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[10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) ->
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[10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) ->
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[10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) ->
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[10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) ->
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[10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) ->
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[10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) ->
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[10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) ->
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[10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) ->
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|
[10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) ->
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|
[10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) ->
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[10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) ->
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[10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) ->
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[10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) ->
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[10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) ->
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[10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) ->
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[10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) ->
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[10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) ->
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[10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) ->
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[10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) ->
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[10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) ->
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[10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) ->
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|
[10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) ->
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|
[10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) ->
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[10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) ->
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|
[10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) ->
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[10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) ->
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[10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) ->
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[10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) ->
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|
[10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) ->
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|
[10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) ->
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|
[10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) ->
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|
[10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) ->
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[10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) ->
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|
[10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) ->
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|
[ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) ->
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|
[10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) ->
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|
[10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) ->
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|
[10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) ->
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[10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) ->
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[10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) ->
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|
[10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) ->
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|
[10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) ->
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|
[10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) ->
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|
[10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) ->
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|
[10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) ->
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|
[10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) ->
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|
[10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) ->
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|
[10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) ->
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|
[10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) ->
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|
[10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) ->
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|
[10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) ->
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|
[10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) ->
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|
[10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) ->
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|
[10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) ->
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|
[10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) ->
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|
[10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) ->
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|
[10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) ->
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|
[10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) ->
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|
[10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) ->
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|
[10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) ->
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|
[ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) ->
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|
[10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) ->
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|
[10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) ->
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|
[10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) ->
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|
[10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) ->
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|
[10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) ->
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|
[10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) ->
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|
[ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) ->
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|
[10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) ->
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|
[10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) ->
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|
[10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) ->
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|
[10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) ->
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|
[10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) ->
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|
[10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) ->
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|
[10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) ->
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|
[10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) ->
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|
[10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) ->
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|
[10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) ->
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|
[10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) ->
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|
[10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) ->
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|
[10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) ->
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|
[10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) ->
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|
[10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) ->
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|
[10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) ->
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|
[10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) ->
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|
[10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) ->
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|
[10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) ->
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|
[10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) ->
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|
[10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) ->
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|
[10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) ->
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|
[10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) ->
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|
[10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) ->
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|
[10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) ->
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|
[10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) ->
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|
[10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) ->
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|
[10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) ->
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|
[10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) ->
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|
[10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) ->
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|
[10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) ->
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|
[10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) ->
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|
[10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) ->
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|
[10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) ->
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|
[10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) ->
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|
[10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) ->
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|
[10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) ->
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|
[10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) ->
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|
[10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) ->
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|
[10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) ->
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|
[10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) ->
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|
[10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) ->
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|
[10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) ->
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|
[10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) ->
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|
[10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) ->
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|
[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) ->
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|
[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) ->
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|
[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) ->
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|
[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) ->
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|
[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) ->
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|
[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) ->
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|
[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) ->
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|
[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) ->
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|
[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) ->
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|
[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) ->
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|
[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) ->
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|
[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) ->
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|
[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) ->
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|
[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) ->
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|
[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) ->
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|
[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) ->
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|
[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) ->
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|
[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) ->
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|
[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) ->
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|
[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) ->
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|
[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) ->
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|
[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) ->
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|
[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) ->
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|
[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) ->
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|
[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) ->
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|
[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) ->
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|
[15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) ->
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|
[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) ->
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|
[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) ->
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|
[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) ->
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|
[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) ->
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|
[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) ->
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|
[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) ->
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|
[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) ->
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|
[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) ->
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|
[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) ->
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|
[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) ->
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|
[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) ->
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|
[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) ->
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|
[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) ->
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|
[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) ->
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|
[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) ->
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|
[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) ->
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|
[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) ->
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|
[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) ->
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|
[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) ->
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|
[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) ->
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|
[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) ->
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|
[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) ->
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|
[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) ->
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|
[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
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|
[ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) ->
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|
[10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) ->
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|
[10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) ->
|
|
[10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) ->
|
|
[10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) ->
|
|
[10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) ->
|
|
[10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) ->
|
|
[10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) ->
|
|
[10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) ->
|
|
[10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) ->
|
|
[10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) ->
|
|
[10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) ->
|
|
[10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) ->
|
|
[10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) ->
|
|
[10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) ->
|
|
[10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) ->
|
|
[10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) ->
|
|
[10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) ->
|
|
[10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) ->
|
|
[10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) ->
|
|
[10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) ->
|
|
[10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) ->
|
|
[10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) ->
|
|
[10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) ->
|
|
[10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) ->
|
|
[10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) ->
|
|
[10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) ->
|
|
[10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) ->
|
|
[10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) ->
|
|
[10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) ->
|
|
[10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) ->
|
|
[10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) ->
|
|
[10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) ->
|
|
[10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) ->
|
|
[10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) ->
|
|
[10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) ->
|
|
[10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) ->
|
|
[10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) ->
|
|
[10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) ->
|
|
[10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) ->
|
|
[10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) ->
|
|
[10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) ->
|
|
[10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) ->
|
|
[10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) ->
|
|
[10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) ->
|
|
[10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) ->
|
|
[10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) ->
|
|
[10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) ->
|
|
[10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) ->
|
|
[10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) ->
|
|
[10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) ->
|
|
[10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) ->
|
|
[10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) ->
|
|
[10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) ->
|
|
[10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) ->
|
|
[10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) ->
|
|
[10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) ->
|
|
[10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) ->
|
|
[10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) ->
|
|
[10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) ->
|
|
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) ->
|
|
[10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) ->
|
|
[10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) ->
|
|
[10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) ->
|
|
[10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) ->
|
|
[10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) ->
|
|
[10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) ->
|
|
[10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) ->
|
|
[10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) ->
|
|
[10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) ->
|
|
[10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) ->
|
|
[10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) ->
|
|
[10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) ->
|
|
[10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) ->
|
|
[10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) ->
|
|
[10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) ->
|
|
[10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) ->
|
|
[ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) ->
|
|
[10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) ->
|
|
[10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) ->
|
|
[10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) ->
|
|
[10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) ->
|
|
[10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) ->
|
|
[10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) ->
|
|
[10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) ->
|
|
[10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) ->
|
|
[10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) ->
|
|
[10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) ->
|
|
[10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) ->
|
|
[10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) ->
|
|
[10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) ->
|
|
[10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) ->
|
|
[10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) ->
|
|
[10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) ->
|
|
[10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) ->
|
|
[10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) ->
|
|
[10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) ->
|
|
[10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) ->
|
|
[10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) ->
|
|
[10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) ->
|
|
[10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) ->
|
|
[10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) ->
|
|
[10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) ->
|
|
[ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) ->
|
|
[10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) ->
|
|
[10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) ->
|
|
[10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) ->
|
|
[10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) ->
|
|
[10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) ->
|
|
[10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) ->
|
|
[10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) ->
|
|
[10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) ->
|
|
[10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) ->
|
|
[10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) ->
|
|
[10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) ->
|
|
[10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) ->
|
|
[10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) ->
|
|
[10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) ->
|
|
[10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) ->
|
|
[10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) ->
|
|
[10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) ->
|
|
[10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) ->
|
|
[10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) ->
|
|
[10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) ->
|
|
[10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) ->
|
|
[10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) ->
|
|
[10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) ->
|
|
[10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) ->
|
|
[10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) ->
|
|
[10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) ->
|
|
[10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) ->
|
|
[10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) ->
|
|
[10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) ->
|
|
[10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) ->
|
|
[10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) ->
|
|
[10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) ->
|
|
[10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) ->
|
|
[10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) ->
|
|
[10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) ->
|
|
[10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) ->
|
|
[10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) ->
|
|
[10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) ->
|
|
[10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) ->
|
|
[10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) ->
|
|
[10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) ->
|
|
[10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) ->
|
|
[10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) ->
|
|
[10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) ->
|
|
[10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) ->
|
|
[10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) ->
|
|
[10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) ->
|
|
[10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) ->
|
|
[10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) ->
|
|
[10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) ->
|
|
[10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) ->
|
|
[10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) ->
|
|
[10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) ->
|
|
[10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) ->
|
|
[10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) ->
|
|
[10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) ->
|
|
[10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) ->
|
|
[10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) ->
|
|
[10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) ->
|
|
[10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) ->
|
|
[10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) ->
|
|
[10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) ->
|
|
[10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) ->
|
|
[10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) ->
|
|
[10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) ->
|
|
[10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) ->
|
|
[10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) ->
|
|
[10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) ->
|
|
[10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) ->
|
|
[10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) ->
|
|
[10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) ->
|
|
[10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) ->
|
|
[10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) ->
|
|
[10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) ->
|
|
[10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) ->
|
|
[10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) ->
|
|
[10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) ->
|
|
[10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) ->
|
|
[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) ->
|
|
[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) ->
|
|
[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) ->
|
|
[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) ->
|
|
[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) ->
|
|
[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) ->
|
|
[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) ->
|
|
[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) ->
|
|
[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) ->
|
|
[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) ->
|
|
[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) ->
|
|
[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) ->
|
|
[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) ->
|
|
[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) ->
|
|
[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) ->
|
|
[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) ->
|
|
[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) ->
|
|
[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) ->
|
|
[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) ->
|
|
[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) ->
|
|
[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) ->
|
|
[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) ->
|
|
[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) ->
|
|
[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) ->
|
|
[ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: LAST ROW
|
|
Number of Operations: 2304
|
|
Time Started: 99430 ns
|
|
Time Done: 124000 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) ->
|
|
[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 124080000.0 ps
|
|
[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) ->
|
|
[10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 10602) -> [10000 ps] ACT @ (0, 11682) -> [17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) ->
|
|
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) ->
|
|
[17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) ->
|
|
[17500 ps] WR @ (0, 944) -> [ 2500 ps] ACT @ (4, 5206) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) ->
|
|
[10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) ->
|
|
[10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) ->
|
|
[10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) ->
|
|
[10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) ->
|
|
[10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) ->
|
|
[17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) ->
|
|
[10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) ->
|
|
[17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) ->
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|
[10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) ->
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|
[17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) ->
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|
[10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) ->
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|
[17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) ->
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|
[10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) ->
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|
[17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) ->
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|
[10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) ->
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|
[17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) ->
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[10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) ->
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[17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) ->
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|
[10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) ->
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|
[17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) ->
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[17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) ->
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|
[10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) ->
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|
[17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) ->
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|
[17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) ->
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[10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) ->
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[17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) ->
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[17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) ->
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[10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) ->
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[17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) ->
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[17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) ->
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[10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) ->
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[17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) ->
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[17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) ->
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|
[10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) ->
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[17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) ->
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[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) ->
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[10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) ->
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|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) ->
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|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) ->
|
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9324) -> [10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) ->
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|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) ->
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[10000 ps] WR @ (0, 784) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) ->
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|
[17500 ps] WR @ (0, 784) -> [ 2500 ps] ACT @ (4, 3928) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) ->
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[10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) ->
|
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[17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) ->
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[10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) ->
|
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[17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) ->
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[10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) ->
|
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[17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) ->
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[10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) ->
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[17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) ->
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[10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) ->
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[17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) ->
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[10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) ->
|
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[17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) ->
|
|
[10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) ->
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[17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) ->
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[17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) ->
|
|
[10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) ->
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[17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) ->
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[17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) ->
|
|
[10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) ->
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[17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) ->
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[17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) ->
|
|
[10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) ->
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|
[17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) ->
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[17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) ->
|
|
[10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) ->
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[17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) ->
|
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[17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) ->
|
|
[10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) ->
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[17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) ->
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[17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) ->
|
|
[10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) ->
|
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[17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) ->
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[10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) ->
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[10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) ->
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[10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) ->
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[10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) ->
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[10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8046) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) ->
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[10000 ps] WR @ (0, 624) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) ->
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[17500 ps] WR @ (0, 624) -> [ 2500 ps] ACT @ (4, 2650) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) ->
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[10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) ->
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[17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) ->
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[10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) ->
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[17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) ->
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[17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) ->
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[10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) ->
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[17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) ->
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[17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) ->
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[10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) ->
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[17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) ->
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[17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) ->
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[10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) ->
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[17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) ->
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[17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) ->
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[10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) ->
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[17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) ->
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[17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) ->
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[10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> [10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) ->
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[17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) ->
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[17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) ->
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[10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> [10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> [10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> [10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) ->
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[10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) ->
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[10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) ->
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[10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) ->
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[10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) ->
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[10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) ->
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[10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) ->
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[10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) ->
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[17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) ->
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[10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) ->
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[17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) ->
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[10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) ->
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[17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) ->
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[10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) ->
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[17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) ->
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[10000 ps] WR @ (0, 464) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) ->
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[10000 ps] ACT @ (4, 2451) -> [ 7500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) ->
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[17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) ->
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[17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) ->
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[10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) ->
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[17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) ->
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[17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) ->
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[10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) ->
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[10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) ->
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[10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) ->
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[10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) ->
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[10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) ->
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[10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) ->
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[10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) ->
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[10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) ->
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[17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) ->
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[10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) ->
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[17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) ->
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[10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) ->
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[17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) ->
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[10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) ->
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[17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) ->
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[10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) ->
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[17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) ->
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[10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) ->
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[17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) ->
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[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) ->
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[10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) ->
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[17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) ->
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[10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) ->
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[17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) ->
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[17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) ->
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[10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) ->
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[17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) ->
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[17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) ->
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|
[10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) ->
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[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) ->
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|
[ 2500 ps] ACT @ (0, 15399) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) ->
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|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> [10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) ->
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|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> [10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> [10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) ->
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[10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) ->
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[10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) ->
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[10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) ->
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[10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) ->
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[10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) ->
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[10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) ->
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[10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) ->
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[17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) ->
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[10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) ->
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[17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) ->
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[10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) ->
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[17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) ->
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[10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) ->
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[17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) ->
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[10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) ->
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[17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) ->
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[10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) ->
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[17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) ->
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[10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) ->
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[17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) ->
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[10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) ->
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[17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) ->
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[17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) ->
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[10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) ->
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[17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) ->
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[17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) ->
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[10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) ->
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[17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) ->
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[17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) ->
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[10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) ->
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[17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) ->
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[17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) ->
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[10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) ->
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[17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) ->
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[17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) ->
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[10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) ->
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[17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) ->
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[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) ->
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[10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> [17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) -> [10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) ->
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[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) ->
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[ 2500 ps] ACT @ (0, 14121) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) ->
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[10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) ->
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[10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) ->
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[10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) ->
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[10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) ->
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[10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) ->
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[17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) ->
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[10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) ->
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[17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) ->
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[10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) ->
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[17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) ->
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[10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) ->
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[17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) ->
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[10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) ->
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[17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) ->
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[10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) ->
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[17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) ->
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[10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) ->
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[17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) ->
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[10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) ->
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[17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) ->
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[17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) ->
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[10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) ->
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[17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) ->
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[17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) ->
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[10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) ->
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[17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) ->
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[17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) ->
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[10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) ->
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[17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) ->
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[17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) ->
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[10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) ->
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[17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) ->
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[17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) ->
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[10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) ->
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[17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) ->
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[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) ->
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[10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) ->
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[ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) ->
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[10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) ->
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[10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) ->
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[17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) ->
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[ 7500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) ->
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[17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) ->
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[ 7500 ps] WR @ (7, 1008) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) ->
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[17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) ->
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[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) ->
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[10000 ps] ACT @ (0, 16081) -> [ 7500 ps] WR @ (3, 1008) -> [ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) -> [10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) -> [10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) ->
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[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) ->
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[10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) ->
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[17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) ->
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[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) ->
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[10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) ->
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[17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) ->
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[10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> [10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) ->
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[17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) ->
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[17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) ->
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[10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) ->
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[17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) ->
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[17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) ->
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[10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) ->
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[17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) ->
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[17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) ->
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[10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> [10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) ->
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[17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) ->
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[17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) ->
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[10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) ->
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[17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) ->
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[17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) ->
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[10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) ->
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[17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) ->
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[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) ->
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[10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) -> [17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
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[ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> [17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) ->
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[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) ->
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[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) -> [10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) ->
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[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) ->
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[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> [10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) ->
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[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) ->
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[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) -> [10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) ->
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[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) ->
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[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> [10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) ->
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[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) ->
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[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) -> [10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) ->
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[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) ->
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[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> [10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) ->
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[10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) ->
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[10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) ->
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[10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9210) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) ->
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[10000 ps] WR @ (3, 848) -> [ 5000 ps] NOP -> [40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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[360000 ps] NOP -> [17500 ps] ACT @ (7, 3814) -> [17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) ->
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[17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) ->
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[17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) ->
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[10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) ->
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[17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) ->
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[17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) ->
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[10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> [17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) -> [17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) -> [10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> [10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) -> [10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> [10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) -> [10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) ->
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[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> [17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) ->
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[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) ->
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[ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) -> [10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) -> [ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> [ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) -> [10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> [10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) -> [10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> [10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) -> [10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> [10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) ->
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[10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) ->
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[10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) ->
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[10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) ->
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[10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) ->
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[10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) ->
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[10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) ->
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[10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) ->
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[15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) ->
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[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) ->
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[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) ->
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[10000 ps] RD @ (4, 848) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) ->
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[10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) ->
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[15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) ->
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[15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) ->
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[10000 ps] ACT @ (0, 10895) -> [ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) ->
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[15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) ->
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[15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) ->
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[10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) ->
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[15000 ps] RD @ (0, 832) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) ->
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[15000 ps] RD @ (0, 832) -> [10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) ->
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[10000 ps] ACT @ (0, 103) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) ->
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[15000 ps] RD @ (0, 824) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) ->
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[15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) ->
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[10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6774) -> [15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4616) -> [10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1378) -> [15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12366) -> [15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 10208) -> [10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6970) -> [15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1574) -> [15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15800) -> [10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12562) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) ->
|
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[10000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2162) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) ->
|
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[10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) ->
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|
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) ->
|
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[10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7754) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) ->
|
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[10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) ->
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|
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) ->
|
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[10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13346) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) ->
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[10000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) ->
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[10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) ->
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[15000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) ->
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[10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) ->
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[ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) ->
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[10000 ps] RD @ (4, 712) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) ->
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[ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) ->
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[10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) ->
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[ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) ->
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[10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) ->
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[ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) ->
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[10000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) ->
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[ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) ->
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[10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) ->
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[ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) ->
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[10000 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) ->
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[15000 ps] RD @ (4, 688) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) ->
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[15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) ->
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[10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) ->
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[15000 ps] RD @ (4, 680) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) ->
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[15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) ->
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[10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) ->
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[15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) ->
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[15000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) ->
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[10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) ->
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[15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) ->
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[15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) ->
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[10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) ->
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[15000 ps] RD @ (4, 664) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) ->
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[15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) ->
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[10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) ->
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[15000 ps] RD @ (4, 656) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) ->
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[15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) ->
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[10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) ->
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[15000 ps] RD @ (0, 624) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) ->
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[15000 ps] RD @ (4, 624) -> [ 5000 ps] ACT @ (0, 492) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) ->
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[10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) ->
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[ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) ->
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[10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) ->
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[ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) ->
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[10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) ->
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[ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) ->
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[10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) ->
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[ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) ->
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[10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) ->
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[ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) ->
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[10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) ->
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[ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) ->
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[10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) ->
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[ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) ->
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[10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) ->
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[15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) ->
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[15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) ->
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[10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) ->
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[15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) ->
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[15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) ->
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[10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) ->
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[15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) ->
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[15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) ->
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[10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) ->
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[15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) ->
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[15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) ->
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[10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) ->
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[15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) ->
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[15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) ->
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[10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) ->
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[15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) ->
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[15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) ->
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[10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> [ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> [ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> [10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> [10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> [10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) -> [10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> [10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) -> [10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) ->
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[10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) ->
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[10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) ->
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[10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) ->
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[10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) ->
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[10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) ->
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[10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) ->
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[10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) ->
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[15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) ->
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[10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) ->
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[ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) ->
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[10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) ->
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[ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) ->
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[10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) ->
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[ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) ->
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[10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) ->
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[ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) ->
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[10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) ->
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[ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) ->
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[10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) ->
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[ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) ->
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[10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> [10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) ->
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[15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) ->
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[15000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) ->
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[10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) ->
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[15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) ->
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[15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) ->
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[10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) ->
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[15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) ->
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[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
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[17500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) -> [10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) -> [ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) -> [10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) -> [10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3627) -> [10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9219) -> [10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) ->
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[10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13732) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) ->
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[10000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) ->
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[10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2940) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) ->
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[10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) ->
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[10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8532) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) ->
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[10000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) ->
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[10000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) ->
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[15000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) ->
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[10000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) ->
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[ 5000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) ->
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[10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) ->
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[ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) ->
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[10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) ->
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[ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) ->
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[10000 ps] RD @ (4, 296) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) ->
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[ 5000 ps] RD @ (4, 296) -> [10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) ->
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[10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) ->
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[ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) ->
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[10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) ->
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[ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) ->
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[10000 ps] ACT @ (0, 14516) -> [15000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) ->
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[15000 ps] RD @ (4, 280) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) ->
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[15000 ps] RD @ (4, 280) -> [10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) ->
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[10000 ps] ACT @ (4, 8040) -> [ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) ->
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[15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) ->
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[15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 272) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) ->
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[10000 ps] ACT @ (4, 2644) -> [ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) ->
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[15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) ->
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[15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) ->
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[10000 ps] ACT @ (4, 13632) -> [ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) ->
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[15000 ps] RD @ (4, 264) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) ->
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[15000 ps] RD @ (4, 264) -> [10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) ->
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[10000 ps] ACT @ (4, 8236) -> [ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) ->
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[15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) ->
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[15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) ->
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[10000 ps] ACT @ (4, 2840) -> [ 5000 ps] RD @ (0, 256) -> [10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) ->
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[15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) ->
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[15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) ->
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[10000 ps] ACT @ (4, 13828) -> [ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10591) -> [15000 ps] RD @ (0, 248) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 7353) -> [10000 ps] ACT @ (0, 6274) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5195) -> [15000 ps] RD @ (0, 240) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4116) -> [15000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 1957) -> [10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16183) -> [15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 12945) -> [10000 ps] ACT @ (0, 11866) -> [ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10787) -> [15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9708) -> [15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 7549) -> [10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5391) -> [15000 ps] RD @ (0, 224) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) -> [10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 2153) -> [10000 ps] ACT @ (0, 1074) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16379) -> [15000 ps] RD @ (0, 216) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15300) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 13141) -> [10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) ->
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[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5587) -> [10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11179) -> [10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 387) -> [10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) ->
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|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP ->
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[ 2500 ps] RD @ (4, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) ->
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|
[15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
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[17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> [ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) ->
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[15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) ->
|
|
[10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) -> [10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) ->
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[15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) ->
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[15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) ->
|
|
[10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) ->
|
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[15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) ->
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[15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) ->
|
|
[10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) ->
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[15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) ->
|
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[15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) ->
|
|
[10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> [10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) ->
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[15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) ->
|
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[15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) ->
|
|
[10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) ->
|
|
[15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) ->
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|
[15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) ->
|
|
[10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) ->
|
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[17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> [10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> [ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) ->
|
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[17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> [ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) ->
|
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[17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) ->
|
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[17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) -> [10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) -> [ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) -> [ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) -> [10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) -> [10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) -> [10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) -> [10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) -> [10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) ->
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[10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) ->
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[10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) ->
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[10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) ->
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[10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) ->
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[10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) ->
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[10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) ->
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[10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) ->
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[15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) ->
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[10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) ->
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[ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) ->
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[10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) ->
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[ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) ->
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[10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) ->
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[ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) ->
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[10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) ->
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[ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) ->
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[10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) ->
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[ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) ->
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[10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) ->
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[ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) ->
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[10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) ->
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[15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) ->
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[15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) ->
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[10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> [10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) ->
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[15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) ->
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[15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) ->
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[10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) -> [10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) ->
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[15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) ->
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[15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) ->
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[ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) ->
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[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) ->
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[27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) ->
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[ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) -> [10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) -> [10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) -> [10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) -> [10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10685) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8526) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7447) -> [10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
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[17500 ps] ACT @ (4, 3130) -> [10000 ps] ACT @ (3, 3130) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> [15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) ->
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[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) ->
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[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) ->
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[ 5000 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) ->
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|
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) ->
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[10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) ->
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[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) ->
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|
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) ->
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|
[10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) ->
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|
[ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) ->
|
|
[10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) ->
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[15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) ->
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[15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) ->
|
|
[10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) ->
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[15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) ->
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[15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) ->
|
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[10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) ->
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[15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) ->
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[15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) ->
|
|
[10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) ->
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|
[15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) ->
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|
[15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) ->
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|
[10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) ->
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|
[15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) ->
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|
[15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) ->
|
|
[10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) ->
|
|
[15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) ->
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|
[15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) ->
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|
[10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
|
|
[ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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|
[ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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|
[ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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|
[ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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|
[ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
|
|
[ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) ->
|
|
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) ->
|
|
[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) ->
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|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) ->
|
|
[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) ->
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|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) ->
|
|
[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) ->
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|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) ->
|
|
[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) ->
|
|
[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) ->
|
|
[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) ->
|
|
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) ->
|
|
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) ->
|
|
[10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) ->
|
|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) ->
|
|
[10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) ->
|
|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) ->
|
|
[10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) ->
|
|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) ->
|
|
[10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) ->
|
|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) ->
|
|
[10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) ->
|
|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) ->
|
|
[10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) ->
|
|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) ->
|
|
[10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) ->
|
|
[15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) ->
|
|
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) ->
|
|
[10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) ->
|
|
[ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) ->
|
|
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) ->
|
|
[10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) ->
|
|
[ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) ->
|
|
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) ->
|
|
[10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) ->
|
|
[ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) ->
|
|
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) ->
|
|
[10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) ->
|
|
[ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) ->
|
|
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) ->
|
|
[10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) ->
|
|
[ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) ->
|
|
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) ->
|
|
[10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) ->
|
|
[ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) ->
|
|
[10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) ->
|
|
[15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) ->
|
|
[15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) ->
|
|
[10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) ->
|
|
[15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) ->
|
|
[15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) ->
|
|
[10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) ->
|
|
[15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) ->
|
|
[15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) ->
|
|
[10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) ->
|
|
[15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) ->
|
|
[15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) ->
|
|
[10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) ->
|
|
[15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) ->
|
|
[15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
|
|
[17500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) ->
|
|
|
|
--------------------------------
|
|
DONE TEST 2: RANDOM
|
|
Number of Operations: 2304
|
|
Time Started: 124100 ns
|
|
Time Done: 233710 ns
|
|
Average Rate: 47 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 233840000.0 ps
|
|
|
|
|
|
------- SUMMARY -------
|
|
Number of Writes = 4608
|
|
Number of Reads = 4608
|
|
Number of Success = 4604
|
|
Number of Fails = 4
|
|
Number of Injected Errors = 4
|
|
|
|
$stop called at time : 234810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
|
|
run: Time (s): cpu = 00:00:15 ; elapsed = 00:44:56 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1358 ; free virtual = 24780
|
|
## quit
|
|
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2640970 ms
|
|
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 15:46:48 2023...
|