14188 lines
2.2 MiB
14188 lines
2.2 MiB
#-----------------------------------------------------------
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# xsim v2021.2 (64-bit)
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# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
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# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
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# Start of session at: Wed Jul 5 14:10:39 2023
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# Process ID: 10147
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# Current directory: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim
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# Command line: xsim -log simulate.log -mode tcl -source {xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl}
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# Log file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/simulate.log
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# Journal file: /home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/xsim.jou
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# Running On: angelo-desktop, OS: Linux, CPU Frequency: 3689.401 MHz, CPU Physical cores: 2, Host memory: 7450 MB
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#-----------------------------------------------------------
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source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
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# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
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Time resolution is 1 ps
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source cmd.tcl
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## set curr_wave [current_wave_config]
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## if { [string length $curr_wave] == 0 } {
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## if { [llength [get_objects]] > 0} {
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## add_wave /
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## set_property needs_save false [current_wave_config]
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## } else {
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## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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## }
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## }
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## run -all
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Test ns_to_cycles() function:
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ns_to_cycles(15) = 3 = 2 [exact]
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ns_to_cycles(14.5) = 3 = 2 [round-off]
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ns_to_cycles(11) = 3 = 2 [round-up]
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Test nCK_to_cycles() function:
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ns_to_cycles(16) = 4 = 4 [exact]
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ns_to_cycles(15) = 4 = 4 [round-off]
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ns_to_cycles(13) = 4 = 4 [round-up]
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Test ns_to_nCK() function:
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ns_to_cycles(15) = 12 = 6 [exact]
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ns_to_cycles(14.875) = 12 = 6 [round-off]
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ns_to_cycles(13.875) = 12 = 6 [round-up]
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ns_to_nCK(tRCD) = 11 = 6 [WRONG]
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tRTP = 7.5 = 10.000000
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ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test $floor() function:
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$floor(5/2) = 2.5 = 2
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$floor(9/4) = 2.25 = 2
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$floor(9/4) = 2 = 2
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$floor(9/5) = 1.8 = 1
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DELAY_COUNTER_WIDTH = 16
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DELAY_SLOT_WIDTH = 19
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serdes_ratio = 4
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wb_addr_bits = 24
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wb_data_bits = 512
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wb_sel_bits = 64
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READ_SLOT = 2
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WRITE_SLOT = 3
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ACTIVATE_SLOT = 0
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PRECHARGE_SLOT = 1
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DELAYS:
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ns_to_nCK(tRCD): 6
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ns_to_nCK(tRP): 6
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ns_to_nCK(tRTP): 4
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tCCD: 4
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(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
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(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
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(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
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$signed(4'b1100)>>>4: 1111
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PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
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ACTIVATE_TO_WRITE_DELAY = 3 = 0
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ACTIVATE_TO_READ_DELAY = 2 = 0
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READ_TO_WRITE_DELAY = 2 = 1
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READ_TO_READ_DELAY = 0 = 0
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READ_TO_PRECHARGE_DELAY = 1 =1
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WRITE_TO_WRITE_DELAY = 0 = 0
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WRITE_TO_READ_DELAY = 4 = 3
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WRITE_TO_PRECHARGE_DELAY = 5 = 4
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STAGE2_DATA_DEPTH = 2 = 2
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READ_ACK_PIPE_WIDTH = 6
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ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
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[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive.
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[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
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[510000 ps] NOP -> [370000 ps] MRS ->
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ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
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[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
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[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
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[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
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[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) ->
|
|
[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) ->
|
|
[247500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43471402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43473902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43476402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43478902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43481402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43483902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43486402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43488902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43491402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43493902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43621480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43623980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43626480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43628980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43631480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43633980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43636480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43638980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43641480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43643980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45582600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45585100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45587600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45590100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45592600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45595100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45722600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45725100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45727600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45730100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45732600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45735100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45737600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45740100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45742600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45745100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46321402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46323902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46326402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46328902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46331402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46333902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46336402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46338902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46341402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46343902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46471480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46473980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46476480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46478980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46481480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46483980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46486480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46488980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46491480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46493980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48432600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48435100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48437600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48440100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48442600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48445100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48582600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48585100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48587600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48590100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48592600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48595100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49171402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49173902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49176402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49178902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49181402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49183902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49186402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49188902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49191402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49193902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49321480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49323980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49326480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49328980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49331480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49333980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49336480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49338980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49341480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49343980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51282600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51285100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51287600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51290100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51292600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51295100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51432600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51435100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51437600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51440100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51442600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51445100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52021402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52023902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52026402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52028902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52031402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52033902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52036402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52038902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52041402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52043902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52171480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52173980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52176480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52178980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52181480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52183980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52186480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52188980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52191480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52193980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54132600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54135100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54137600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54140100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54142600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54145100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54282600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54285100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54287600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54290100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54292600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54295100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54871402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54873902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54876402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54878902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54881402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54883902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54886402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54888902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54891402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54893902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55021480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55023980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55026480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55028980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55031480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55033980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55036480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55038980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55041480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55043980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56982600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56985100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56987600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56990100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56992600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56995100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57132600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57135100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57137600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57140100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57142600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57145100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57721402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57723902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57726402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57728902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57731402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57733902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57736402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57738902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57741402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57743902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57871480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57873980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57876480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57878980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57881480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57883980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57886480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57888980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57891480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57893980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59832600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59835100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59837600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59840100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59842600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59845100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59982600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59985100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59987600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59990100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59992600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59995100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60571402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60573902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60576402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60578902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60581402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60583902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60586402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60588902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60591402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60593902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60721480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60723980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60726480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60728980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60731480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60733980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60736480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60738980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60741480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60743980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62682600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62685100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62687600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62690100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62692600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62695100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62832600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62835100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62837600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62840100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62842600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62845100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63421402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63423902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63426402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63428902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63431402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63433902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63436402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63438902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63441402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63443902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63571480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63573980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63576480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63578980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63581480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63583980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63586480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63588980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63591480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63593980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65522600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65525100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65527600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65530100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65532600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65535100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65537600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65540100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65542600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65545100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65682600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65685100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65687600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65690100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65692600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65695100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
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[22670000 ps] MRS ->
|
|
[10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [37500 ps] ACT @ (0, 0) ->
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|
[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
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|
[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
|
|
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
|
|
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
|
|
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
|
|
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
|
|
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
|
|
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
|
|
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
|
|
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
|
|
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
|
|
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
|
|
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
|
|
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
|
|
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
|
|
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
|
|
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
|
|
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
|
|
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
|
|
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
|
|
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
|
|
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
|
|
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
|
|
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
|
|
[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
|
|
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
|
|
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
|
|
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
|
|
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
|
|
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
|
|
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
|
|
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
|
|
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
|
|
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
|
|
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
|
|
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
|
|
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
|
|
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
|
|
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
|
|
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
|
|
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
|
|
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
|
|
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
|
|
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
|
|
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
|
|
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
|
|
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
|
|
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
|
|
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
|
|
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) ->
|
|
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
|
|
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
|
|
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
|
|
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
|
|
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
|
|
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
|
|
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
|
|
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
|
|
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
|
|
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
|
|
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
|
|
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
|
|
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
|
|
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
|
|
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
|
|
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
|
|
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
|
|
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
|
|
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
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|
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
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|
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
|
|
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
|
|
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
|
|
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
|
|
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
|
|
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) ->
|
|
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
|
|
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
|
|
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
|
|
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
|
|
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
|
|
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
|
|
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
|
|
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
|
|
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
|
|
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
|
|
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
|
|
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
|
|
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
|
|
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
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|
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
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|
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
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[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
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[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
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[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
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|
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
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|
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
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|
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
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|
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
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|
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
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|
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
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|
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
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|
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
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|
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
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|
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
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|
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
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|
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
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|
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
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|
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
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|
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
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|
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
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|
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
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|
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
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|
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
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|
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
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|
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
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|
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
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|
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
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|
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
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|
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
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|
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
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|
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
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|
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
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|
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
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|
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
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|
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
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|
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
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|
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
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|
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
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|
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
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|
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
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|
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
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|
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
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|
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
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|
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
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|
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
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|
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
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|
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
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|
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
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|
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
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|
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
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|
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
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|
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
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|
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
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|
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
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|
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
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|
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
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|
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
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|
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
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|
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
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|
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [ 5000 ps] NOP ->
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|
[ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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|
[360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) ->
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|
[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
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|
[ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
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|
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
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|
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
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|
[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) ->
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|
[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
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|
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
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|
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
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|
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
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|
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
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|
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
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|
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
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|
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
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|
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
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|
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
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|
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
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|
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
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|
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
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|
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
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|
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
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|
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
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|
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
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|
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
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|
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
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|
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
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|
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
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|
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) ->
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|
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
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|
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
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|
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
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|
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
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|
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
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|
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
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|
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
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|
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
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|
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
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|
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
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|
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
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|
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
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|
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
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|
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
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|
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
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|
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
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|
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
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|
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
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|
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
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|
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
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|
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
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|
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
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|
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
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|
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
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|
[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
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|
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) ->
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|
[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
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[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
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[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
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[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
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[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
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[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
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[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
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[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
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[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
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[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
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[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
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[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
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[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
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[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
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|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
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[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
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|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
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[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
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[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
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|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
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|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
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|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
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|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
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|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
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|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
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|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
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|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
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|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
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|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
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|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
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|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
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|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
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|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
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|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
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|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
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|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
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|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
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|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
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|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
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|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
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|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
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|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
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|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
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|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
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|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
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|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
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|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
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|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
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|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
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|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
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|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
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|
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
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|
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
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|
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
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|
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
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|
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
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|
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
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|
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
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|
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
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|
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
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|
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
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|
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
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|
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
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|
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
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|
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
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|
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
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|
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
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|
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
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|
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
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|
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
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|
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
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|
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
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|
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
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|
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
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|
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
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|
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
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|
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) ->
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|
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
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|
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
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|
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
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|
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
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|
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
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|
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
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|
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
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|
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
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|
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
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|
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
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|
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
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|
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
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|
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
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|
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
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|
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
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|
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
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|
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
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|
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
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|
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
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|
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
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|
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
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|
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
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|
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
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|
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
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|
[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) ->
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|
[10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (2, 0) ->
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|
[15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
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|
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
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|
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
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|
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
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|
[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) ->
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|
[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
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|
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
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|
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
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|
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
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|
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
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|
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
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|
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
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|
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
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|
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
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|
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
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|
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
|
|
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
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|
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
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|
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
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|
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
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|
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
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|
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
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|
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
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|
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
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|
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
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|
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
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|
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
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|
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
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|
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
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|
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
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|
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
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|
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
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|
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
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|
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
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|
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
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|
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
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|
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
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|
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
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|
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
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|
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
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|
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
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|
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
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|
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
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|
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
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|
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
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|
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
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|
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
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|
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
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|
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
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|
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
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|
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
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|
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
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|
[ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
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|
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
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|
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
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|
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
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|
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
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|
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
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|
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
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|
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
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|
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
|
|
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
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|
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
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|
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
|
|
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
|
|
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
|
|
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
|
|
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
|
|
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
|
|
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
|
|
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
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|
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
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|
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
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|
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
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|
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
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|
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
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|
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
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|
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) ->
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|
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
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|
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
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|
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
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|
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
|
|
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
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|
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
|
|
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
|
|
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
|
|
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
|
|
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
|
|
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
|
|
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
|
|
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
|
|
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
|
|
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
|
|
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
|
|
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
|
|
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
|
|
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
|
|
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
|
|
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
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|
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
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|
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
|
|
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
|
|
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
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|
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) ->
|
|
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
|
|
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
|
|
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
|
|
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
|
|
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
|
|
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
|
|
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
|
|
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
|
|
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
|
|
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
|
|
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
|
|
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
|
|
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
|
|
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
|
|
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
|
|
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
|
|
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
|
|
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
|
|
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
|
|
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
|
|
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
|
|
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
|
|
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
|
|
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
|
|
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
|
|
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
|
|
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
|
|
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
|
|
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
|
|
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
|
|
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
|
|
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
|
|
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
|
|
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
|
|
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
|
|
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
|
|
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
|
|
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
|
|
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
|
|
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
|
|
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
|
|
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
|
|
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
|
|
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
|
|
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
|
|
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
|
|
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
|
|
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
|
|
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
|
|
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
|
|
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
|
|
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: FIRST ROW
|
|
Number of Operations: 2304
|
|
Time Started: 66650 ns
|
|
Time Done: 90740 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) ->
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [27500 ps] NOP -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 90820000.0 ps
|
|
[70000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
|
|
[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
|
|
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
|
|
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
|
|
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
|
|
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
|
|
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
|
|
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
|
|
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
|
|
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
|
|
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
|
|
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
|
|
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
|
|
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
|
|
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
|
|
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
|
|
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
|
|
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
|
|
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
|
|
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
|
|
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
|
|
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
|
|
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
|
|
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
|
|
[ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
|
|
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
|
|
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
|
|
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
|
|
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
|
|
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
|
|
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
|
|
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
|
|
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
|
|
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
|
|
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
|
|
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
|
|
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
|
|
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
|
|
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
|
|
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
|
|
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
|
|
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
|
|
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
|
|
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
|
|
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
|
|
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
|
|
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
|
|
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
|
|
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
|
|
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) ->
|
|
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
|
|
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
|
|
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
|
|
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
|
|
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
|
|
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
|
|
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
|
|
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
|
|
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
|
|
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
|
|
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
|
|
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
|
|
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
|
|
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
|
|
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
|
|
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
|
|
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
|
|
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
|
|
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
|
|
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
|
|
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
|
|
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
|
|
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
|
|
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
|
|
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
|
|
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) ->
|
|
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
|
|
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
|
|
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
|
|
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
|
|
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
|
|
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
|
|
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
|
|
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
|
|
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
|
|
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
|
|
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
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|
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
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|
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
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|
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
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|
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
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|
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
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|
[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
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|
[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
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|
[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
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|
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
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|
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
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|
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
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|
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
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|
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
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|
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
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|
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
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|
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
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|
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
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|
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
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|
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
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|
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
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|
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
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|
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
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|
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
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|
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
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|
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
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|
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
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|
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
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|
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
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|
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
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|
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
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|
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
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|
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
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|
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
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|
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
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|
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
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|
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
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|
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
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|
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
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|
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
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|
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
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|
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
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|
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
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|
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
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|
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
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|
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
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|
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
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|
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
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|
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
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|
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
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|
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
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|
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
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|
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
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|
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
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|
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
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|
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
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|
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
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|
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
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|
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
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|
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
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|
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
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|
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
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|
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
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|
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
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|
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) ->
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|
[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) ->
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|
[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
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|
[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
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|
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
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|
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
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|
[10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) ->
|
|
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 96) ->
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|
[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
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|
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
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|
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
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|
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
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|
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
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|
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
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|
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
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|
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
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|
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
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|
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
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|
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
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|
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
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|
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
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|
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
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|
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
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|
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
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|
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
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|
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
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|
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
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|
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
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|
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
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|
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) ->
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|
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
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|
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
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|
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
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|
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
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|
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
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|
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
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|
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
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|
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
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|
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
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|
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
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|
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
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|
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
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|
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
|
|
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
|
|
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
|
|
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
|
|
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
|
|
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
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|
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
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|
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
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|
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
|
|
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
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|
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
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|
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
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[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
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|
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) ->
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[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
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[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
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[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
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[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
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[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
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[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
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[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
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[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
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[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
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[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
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[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
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[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
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|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
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|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
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|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
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|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
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|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
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[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
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[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
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[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
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[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
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[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
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|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
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[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
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[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
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|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
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|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
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|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
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|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
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|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
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|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
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|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
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|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
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|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
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|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
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|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
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|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
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|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
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|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
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|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
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|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
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|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
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|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
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|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
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|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
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|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
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|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
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|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
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|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
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|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
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|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
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|
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
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|
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
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|
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
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|
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
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|
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
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|
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
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|
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
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|
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
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|
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
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|
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
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|
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
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|
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
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|
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
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|
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
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|
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
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|
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
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|
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
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|
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
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|
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
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|
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
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|
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
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|
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
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|
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
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|
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
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|
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
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|
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) ->
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|
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
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|
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
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|
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
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|
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
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|
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
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|
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
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|
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
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|
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
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|
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
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|
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
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|
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
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|
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
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|
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
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|
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
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|
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
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|
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
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|
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
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|
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
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|
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
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|
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
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|
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
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|
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
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|
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
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|
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
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|
[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) ->
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|
[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
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|
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
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|
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
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|
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
|
|
[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP ->
|
|
[ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> [30000 ps] REF ->
|
|
[360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
|
|
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
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|
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
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|
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
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|
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
|
|
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
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|
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
|
|
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
|
|
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
|
|
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
|
|
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
|
|
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
|
|
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
|
|
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
|
|
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
|
|
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
|
|
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
|
|
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
|
|
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
|
|
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
|
|
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
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|
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
|
|
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
|
|
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
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|
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
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|
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
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|
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
|
|
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
|
|
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
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|
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
|
|
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
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|
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
|
|
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
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|
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
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|
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
|
|
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
|
|
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
|
|
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
|
|
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
|
|
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
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|
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
|
|
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
|
|
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
|
|
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
|
|
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
|
|
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
|
|
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
|
|
[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
|
|
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
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|
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
|
|
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
|
|
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
|
|
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
|
|
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
|
|
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
|
|
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
|
|
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
|
|
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
|
|
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
|
|
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
|
|
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
|
|
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
|
|
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
|
|
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
|
|
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
|
|
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
|
|
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
|
|
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
|
|
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
|
|
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
|
|
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
|
|
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
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|
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) ->
|
|
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
|
|
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
|
|
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
|
|
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
|
|
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
|
|
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
|
|
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
|
|
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
|
|
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
|
|
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
|
|
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
|
|
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
|
|
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
|
|
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
|
|
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
|
|
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
|
|
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
|
|
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
|
|
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
|
|
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
|
|
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
|
|
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
|
|
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
|
|
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
|
|
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
|
|
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) ->
|
|
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
|
|
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
|
|
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
|
|
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
|
|
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
|
|
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
|
|
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
|
|
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
|
|
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
|
|
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
|
|
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
|
|
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
|
|
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
|
|
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
|
|
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
|
|
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
|
|
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
|
|
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
|
|
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
|
|
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
|
|
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
|
|
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
|
|
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
|
|
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
|
|
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
|
|
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
|
|
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
|
|
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
|
|
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
|
|
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
|
|
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
|
|
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
|
|
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
|
|
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
|
|
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
|
|
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
|
|
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
|
|
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
|
|
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
|
|
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
|
|
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
|
|
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
|
|
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
|
|
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
|
|
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
|
|
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
|
|
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
|
|
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
|
|
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
|
|
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
|
|
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
|
|
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: MIDDLE ROW
|
|
Number of Operations: 2304
|
|
Time Started: 90840 ns
|
|
Time Done: 115330 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) ->
|
|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 115410000.0 ps
|
|
[97500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) ->
|
|
[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
|
|
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
|
|
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
|
|
[10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) ->
|
|
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 152) ->
|
|
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
|
|
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
|
|
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
|
|
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
|
|
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
|
|
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
|
|
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
|
|
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
|
|
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
|
|
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
|
|
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
|
|
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
|
|
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
|
|
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
|
|
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
|
|
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
|
|
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
|
|
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
|
|
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
|
|
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) ->
|
|
[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) ->
|
|
[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) ->
|
|
[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) ->
|
|
[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) ->
|
|
[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) ->
|
|
[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) ->
|
|
[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) ->
|
|
[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) ->
|
|
[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) ->
|
|
[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) ->
|
|
[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) ->
|
|
[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) ->
|
|
[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) ->
|
|
[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) ->
|
|
[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) ->
|
|
[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) ->
|
|
[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) ->
|
|
[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) ->
|
|
[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) ->
|
|
[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) ->
|
|
[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) ->
|
|
[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) ->
|
|
[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) ->
|
|
[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) ->
|
|
[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) ->
|
|
[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) ->
|
|
[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) ->
|
|
[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) ->
|
|
[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) ->
|
|
[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) ->
|
|
[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) ->
|
|
[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) ->
|
|
[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) ->
|
|
[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) ->
|
|
[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) ->
|
|
[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) ->
|
|
[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) ->
|
|
[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) ->
|
|
[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) ->
|
|
[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) ->
|
|
[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) ->
|
|
[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) ->
|
|
[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) ->
|
|
[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) ->
|
|
[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) ->
|
|
[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) ->
|
|
[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) ->
|
|
[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) ->
|
|
[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) ->
|
|
[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) ->
|
|
[ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) ->
|
|
[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) ->
|
|
[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) ->
|
|
[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) ->
|
|
[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) ->
|
|
[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) ->
|
|
[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) ->
|
|
[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) ->
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[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) ->
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[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) ->
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[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) ->
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[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) ->
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[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) ->
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[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) ->
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[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) ->
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[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) ->
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[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) ->
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[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) ->
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[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) ->
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[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) ->
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[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) ->
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[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) ->
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[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) ->
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|
[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) ->
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[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) ->
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[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) ->
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[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) ->
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[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) ->
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[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) ->
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[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) ->
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[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) ->
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[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) ->
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[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) ->
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[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) ->
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[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) ->
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[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) ->
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[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) ->
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[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) ->
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[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) ->
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[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) ->
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|
[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) ->
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[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) ->
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[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) ->
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|
[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) ->
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[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) ->
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[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) ->
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|
[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) ->
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|
[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) ->
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[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) ->
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[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) ->
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[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) ->
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|
[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) ->
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|
[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) ->
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[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) ->
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|
[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) ->
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|
[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) ->
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|
[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) ->
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|
[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) ->
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[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) ->
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|
[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) ->
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|
[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) ->
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|
[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) ->
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|
[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) ->
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|
[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) ->
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|
[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) ->
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|
[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) ->
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|
[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) ->
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|
[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) ->
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|
[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) ->
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|
[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) ->
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[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) ->
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|
[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) ->
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[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) ->
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|
[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) ->
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[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) ->
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|
[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) ->
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[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) ->
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|
[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) ->
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|
[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) ->
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|
[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) ->
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|
[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) ->
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|
[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) ->
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|
[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) ->
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|
[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) ->
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|
[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 232) ->
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|
[10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
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|
[17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) ->
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|
[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) ->
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|
[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) ->
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|
[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) ->
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|
[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) ->
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|
[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) ->
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|
[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) ->
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|
[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) ->
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|
[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) ->
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|
[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) ->
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[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) ->
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|
[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) ->
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|
[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) ->
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[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) ->
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|
[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) ->
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|
[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) ->
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|
[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) ->
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|
[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) ->
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|
[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) ->
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|
[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) ->
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|
[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) ->
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[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) ->
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|
[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) ->
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|
[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) ->
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|
[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) ->
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|
[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) ->
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|
[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) ->
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|
[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) ->
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|
[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) ->
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|
[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) ->
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|
[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) ->
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|
[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) ->
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|
[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) ->
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|
[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) ->
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|
[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) ->
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|
[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) ->
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|
[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) ->
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|
[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) ->
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|
[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) ->
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|
[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) ->
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|
[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) ->
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|
[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) ->
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|
[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) ->
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|
[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) ->
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|
[ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) ->
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|
[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
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|
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
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|
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
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|
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
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|
[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
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|
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
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|
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
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|
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
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|
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
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|
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
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|
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
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|
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
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|
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
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|
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
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|
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
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|
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
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|
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
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|
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
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|
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
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|
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
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|
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
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|
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
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|
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
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|
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
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|
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) ->
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|
[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) ->
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|
[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) ->
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|
[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) ->
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|
[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) ->
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|
[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) ->
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|
[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) ->
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|
[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) ->
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|
[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) ->
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|
[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) ->
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|
[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) ->
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|
[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) ->
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|
[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) ->
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|
[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) ->
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|
[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) ->
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|
[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) ->
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|
[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) ->
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|
[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) ->
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|
[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) ->
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|
[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) ->
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|
[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) ->
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|
[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) ->
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|
[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) ->
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|
[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) ->
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|
[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) ->
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|
[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) ->
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|
[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) ->
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|
[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) ->
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|
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) ->
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|
[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) ->
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|
[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) ->
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|
[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) ->
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|
[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) ->
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|
[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) ->
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|
[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) ->
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|
[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) ->
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|
[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) ->
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|
[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) ->
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|
[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) ->
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|
[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) ->
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|
[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) ->
|
|
[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) ->
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|
[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) ->
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|
[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) ->
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|
[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) ->
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|
[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) ->
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|
[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) ->
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|
[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) ->
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|
[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) ->
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|
[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) ->
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|
[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) ->
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|
[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) ->
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|
[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) ->
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|
[ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) ->
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|
[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) ->
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|
[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) ->
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|
[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) ->
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|
[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) ->
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|
[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) ->
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|
[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) ->
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|
[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) ->
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|
[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) ->
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|
[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) ->
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|
[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) ->
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|
[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) ->
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|
[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) ->
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|
[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) ->
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|
[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) ->
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|
[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) ->
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|
[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) ->
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|
[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) ->
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|
[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) ->
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|
[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) ->
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|
[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) ->
|
|
[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) ->
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|
[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) ->
|
|
[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) ->
|
|
[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) ->
|
|
[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) ->
|
|
[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) ->
|
|
[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) ->
|
|
[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) ->
|
|
[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) ->
|
|
[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) ->
|
|
[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) ->
|
|
[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) ->
|
|
[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) ->
|
|
[10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) ->
|
|
[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 304) ->
|
|
[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) ->
|
|
[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) ->
|
|
[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) ->
|
|
[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) ->
|
|
[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) ->
|
|
[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) ->
|
|
[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) ->
|
|
[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) ->
|
|
[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) ->
|
|
[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) ->
|
|
[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) ->
|
|
[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) ->
|
|
[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) ->
|
|
[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) ->
|
|
[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) ->
|
|
[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) ->
|
|
[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) ->
|
|
[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) ->
|
|
[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) ->
|
|
[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) ->
|
|
[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) ->
|
|
[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) ->
|
|
[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) ->
|
|
[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) ->
|
|
[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) ->
|
|
[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) ->
|
|
[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) ->
|
|
[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) ->
|
|
[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) ->
|
|
[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) ->
|
|
[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) ->
|
|
[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) ->
|
|
[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) ->
|
|
[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) ->
|
|
[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) ->
|
|
[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) ->
|
|
[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) ->
|
|
[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) ->
|
|
[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) ->
|
|
[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) ->
|
|
[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) ->
|
|
[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) ->
|
|
[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) ->
|
|
[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) ->
|
|
[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) ->
|
|
[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) ->
|
|
[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) ->
|
|
[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) ->
|
|
[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) ->
|
|
[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) ->
|
|
[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) ->
|
|
[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) ->
|
|
[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) ->
|
|
[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) ->
|
|
[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) ->
|
|
[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) ->
|
|
[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) ->
|
|
[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) ->
|
|
[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) ->
|
|
[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) ->
|
|
[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) ->
|
|
[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) ->
|
|
[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) ->
|
|
[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) ->
|
|
[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) ->
|
|
[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) ->
|
|
[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) ->
|
|
[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) ->
|
|
[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) ->
|
|
[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) ->
|
|
[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) ->
|
|
[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) ->
|
|
[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) ->
|
|
[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) ->
|
|
[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) ->
|
|
[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) ->
|
|
[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) ->
|
|
[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) ->
|
|
[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) ->
|
|
[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) ->
|
|
[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) ->
|
|
[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) ->
|
|
[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) ->
|
|
[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) ->
|
|
[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) ->
|
|
[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) ->
|
|
[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) ->
|
|
[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) ->
|
|
[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) ->
|
|
[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) ->
|
|
[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) ->
|
|
[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) ->
|
|
[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) ->
|
|
[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) ->
|
|
[ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) ->
|
|
[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) ->
|
|
[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) ->
|
|
[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) ->
|
|
[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) ->
|
|
[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) ->
|
|
[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) ->
|
|
[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) ->
|
|
[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) ->
|
|
[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) ->
|
|
[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) ->
|
|
[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) ->
|
|
[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) ->
|
|
[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) ->
|
|
[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) ->
|
|
[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) ->
|
|
[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) ->
|
|
[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) ->
|
|
[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) ->
|
|
[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) ->
|
|
[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) ->
|
|
[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) ->
|
|
[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) ->
|
|
[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) ->
|
|
[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) ->
|
|
[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) ->
|
|
[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) ->
|
|
[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
|
|
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
|
|
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
|
|
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
|
|
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
|
|
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
|
|
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
|
|
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
|
|
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
|
|
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
|
|
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
|
|
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
|
|
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
|
|
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
|
|
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
|
|
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
|
|
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
|
|
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
|
|
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
|
|
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
|
|
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
|
|
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
|
|
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
|
|
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) ->
|
|
[10000 ps] RD @ (0, 984) ->
|
|
--------------------------------
|
|
DONE TEST 1: LAST ROW
|
|
Number of Operations: 2304
|
|
Time Started: 115430 ns
|
|
Time Done: 140000 ns
|
|
Average Rate: 10 ns/request
|
|
--------------------------------
|
|
|
|
|
|
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) ->
|
|
FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 140080000.0 ps
|
|
[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) ->
|
|
[10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) ->
|
|
[17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) ->
|
|
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) ->
|
|
[10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10602) -> [10000 ps] ACT @ (0, 11682) ->
|
|
[17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) ->
|
|
[17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) ->
|
|
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) -> [17500 ps] WR @ (0, 944) -> [ 2500 ps] ACT @ (4, 5206) ->
|
|
[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) ->
|
|
[17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
|
|
[ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) ->
|
|
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) ->
|
|
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) ->
|
|
[10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) ->
|
|
[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) ->
|
|
[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) ->
|
|
[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) ->
|
|
[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) ->
|
|
[17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) ->
|
|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) ->
|
|
[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) ->
|
|
[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) ->
|
|
[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) ->
|
|
[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) ->
|
|
[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) ->
|
|
[10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) ->
|
|
[17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) ->
|
|
[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) ->
|
|
[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) ->
|
|
[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) ->
|
|
[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) ->
|
|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) ->
|
|
[10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) ->
|
|
[17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) ->
|
|
[10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) ->
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[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) ->
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[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) ->
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[10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) ->
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[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) ->
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[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) ->
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[10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) ->
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[17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) ->
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[17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) ->
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[10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) ->
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[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) ->
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[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) ->
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[10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) ->
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[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) ->
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[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) ->
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[10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) ->
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[17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) ->
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[17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9324) ->
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[10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [65000 ps] PRE @ (0) ->
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|
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> [ 2500 ps] ACT @ (4, 3928) ->
|
|
[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) ->
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|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) ->
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|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) ->
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[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) ->
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|
[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) ->
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[10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) ->
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|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) ->
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[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) ->
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[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) ->
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|
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) ->
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[10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) ->
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[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) ->
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[17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) ->
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[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) ->
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[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) ->
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[10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) ->
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[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) ->
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[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) ->
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[17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) ->
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[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) ->
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[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) ->
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[10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) ->
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[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) ->
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|
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) ->
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[10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) ->
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[17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) ->
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[10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) ->
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[17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) ->
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[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) ->
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[10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) ->
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[17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) ->
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[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) ->
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[10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) ->
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[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) ->
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[17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) ->
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[10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) ->
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[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) ->
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[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) ->
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[10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) ->
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[17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) ->
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[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) ->
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[10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) ->
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[17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) ->
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[17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) ->
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[10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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|
[ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
|
|
[ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [65000 ps] PRE @ (0) ->
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|
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> [ 2500 ps] ACT @ (4, 2650) ->
|
|
[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) ->
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[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) ->
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[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) ->
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[10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) ->
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[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) ->
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[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) ->
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[10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) ->
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[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) ->
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[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) ->
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[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) ->
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[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) ->
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[10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) ->
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[17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) ->
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[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) ->
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[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) ->
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[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) ->
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[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) ->
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[10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) ->
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[17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) ->
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[10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) ->
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[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) ->
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[10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) ->
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[17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) ->
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[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) ->
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[10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) ->
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[17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) ->
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[17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) ->
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[10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) ->
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[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) ->
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[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) ->
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[10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) ->
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[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) ->
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[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) ->
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[10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) ->
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[17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) ->
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[17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) ->
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[10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) ->
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[17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) ->
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[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) ->
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[10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> [65000 ps] PRE @ (0) ->
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[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 7500 ps] WR @ (0, 464) ->
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[10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) ->
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[10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) ->
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[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) ->
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[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) ->
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[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) ->
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[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) ->
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[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) ->
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[17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) ->
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[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) ->
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[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) ->
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[10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) ->
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[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) ->
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[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) ->
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[17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) ->
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[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) ->
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[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) ->
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[10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) ->
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[17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) ->
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[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) ->
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[10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) ->
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[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) ->
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[17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) ->
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[10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) ->
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[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) ->
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[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) ->
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[10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) ->
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[17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) ->
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[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) ->
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[10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) ->
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[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) ->
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[17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) ->
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[10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) ->
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[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) ->
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[17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) ->
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[10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) ->
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[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) ->
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[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) ->
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[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) ->
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[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> [10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) ->
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[10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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[360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 15399) -> [42500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) ->
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[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) ->
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[17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) ->
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[10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) ->
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[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) ->
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[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) ->
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[10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) ->
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[17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) ->
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[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) ->
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[10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) ->
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[10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) ->
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[10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) ->
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[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) ->
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[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) ->
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[10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) ->
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[10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) ->
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[10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) ->
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[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) ->
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[10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) ->
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[17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) ->
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[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) ->
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[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) ->
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[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) ->
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[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) ->
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[10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) ->
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[17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) ->
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[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) ->
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[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) ->
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[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) ->
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[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) ->
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[10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) ->
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[17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) ->
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[17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) ->
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[10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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[360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [ 2500 ps] ACT @ (0, 14121) -> [42500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) ->
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[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) ->
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[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) ->
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[10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) ->
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[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) ->
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[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) ->
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[10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) ->
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[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) ->
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[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) ->
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[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) ->
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[10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) ->
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[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) ->
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[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) ->
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[17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) ->
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[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) ->
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[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) ->
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[10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) ->
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[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) ->
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[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) ->
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[17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) ->
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[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) ->
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[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) ->
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[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) ->
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[10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) ->
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[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) ->
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[10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) ->
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[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) ->
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[17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) ->
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[10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) ->
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[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) ->
|
|
[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) ->
|
|
[10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) ->
|
|
[17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) ->
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|
[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) ->
|
|
[ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) ->
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|
[17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) ->
|
|
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) ->
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|
[ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) ->
|
|
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) ->
|
|
[ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) ->
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|
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) ->
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|
[17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) ->
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|
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 7500 ps] WR @ (7, 1008) -> [35000 ps] PRE @ (0) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (4) ->
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|
[17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) ->
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|
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
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|
[360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) -> [10000 ps] ACT @ (0, 16081) -> [ 7500 ps] WR @ (3, 1008) ->
|
|
[ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) ->
|
|
[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) ->
|
|
[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) ->
|
|
[10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) ->
|
|
[10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) ->
|
|
[10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) ->
|
|
[10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) ->
|
|
[10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) ->
|
|
[10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) ->
|
|
[10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) ->
|
|
[10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) ->
|
|
[10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) ->
|
|
[10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) ->
|
|
[17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) ->
|
|
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) ->
|
|
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) ->
|
|
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) ->
|
|
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) ->
|
|
[10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) ->
|
|
[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) ->
|
|
[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) ->
|
|
[10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) ->
|
|
[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) ->
|
|
[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) ->
|
|
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) ->
|
|
[10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) ->
|
|
[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) ->
|
|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) ->
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|
[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) ->
|
|
[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) ->
|
|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) ->
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[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) ->
|
|
[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) ->
|
|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) ->
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[10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) ->
|
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[17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) ->
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|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) ->
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[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) ->
|
|
[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) ->
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|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) ->
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[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) ->
|
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[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) ->
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|
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) ->
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[10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) ->
|
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[17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) ->
|
|
[10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) ->
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[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) ->
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[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) ->
|
|
[10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) ->
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[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) ->
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[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) ->
|
|
[10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) ->
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[17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) ->
|
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[17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) ->
|
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[10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) ->
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[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) ->
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[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) ->
|
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[10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) ->
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[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) ->
|
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[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) ->
|
|
[10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) ->
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[17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) ->
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[17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) ->
|
|
[10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) ->
|
|
[17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) ->
|
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[17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) ->
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|
[17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
|
[ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [ 5000 ps] NOP ->
|
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[40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) ->
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[17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 3814) ->
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[17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) ->
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[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) ->
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[10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) ->
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[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) ->
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[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) ->
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[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) ->
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[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) ->
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[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) ->
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[10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) ->
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[17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) ->
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[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) ->
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[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) ->
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[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) ->
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[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) ->
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[10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) ->
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[17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) ->
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[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) ->
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[10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) ->
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[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) ->
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[10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) ->
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[17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) ->
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[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) ->
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[10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) ->
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[17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) ->
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[17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) ->
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[10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) ->
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[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) ->
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[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) ->
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[10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) ->
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[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) ->
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[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) ->
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[10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) ->
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[17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) ->
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[17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) ->
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[10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) ->
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[17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) ->
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[17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) ->
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[10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) ->
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[15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) ->
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[10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) ->
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[ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) ->
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[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) ->
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[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) ->
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[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) ->
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[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) ->
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[10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) ->
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[ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) ->
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[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) ->
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[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) ->
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[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) ->
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[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) ->
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[10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) ->
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[15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) ->
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[15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) ->
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[10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) ->
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[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) ->
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[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) ->
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[10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) ->
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[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) ->
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[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) ->
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[10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) ->
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[15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) ->
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[15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) ->
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[10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) ->
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[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) ->
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[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) ->
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[10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) ->
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[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) ->
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[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) ->
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[10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> [67500 ps] PRE @ (0) ->
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[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) ->
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[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 840) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> [ 5000 ps] RD @ (4, 840) ->
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[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) ->
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[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> [10000 ps] RD @ (4, 832) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> [ 5000 ps] RD @ (4, 832) ->
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[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) ->
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[10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) ->
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[15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [15000 ps] RD @ (4, 816) ->
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[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> [10000 ps] ACT @ (4, 3536) ->
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[ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [15000 ps] RD @ (4, 816) ->
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[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) ->
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[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [15000 ps] RD @ (4, 808) ->
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[10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> [10000 ps] ACT @ (4, 9128) ->
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[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [15000 ps] RD @ (4, 800) ->
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[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) ->
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[ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [15000 ps] RD @ (4, 800) ->
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[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> [10000 ps] ACT @ (4, 14720) ->
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[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [15000 ps] RD @ (4, 792) ->
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[10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) ->
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[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) ->
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[10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) ->
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[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) ->
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[15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2849) ->
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[10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) ->
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[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) ->
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[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) ->
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[10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) ->
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[15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) ->
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[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8441) ->
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[10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) ->
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[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) ->
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[15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) ->
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[10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) ->
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[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) ->
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[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14033) ->
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[10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) ->
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[15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) ->
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[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) ->
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[10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) ->
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[10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) ->
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[10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) ->
|
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[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) ->
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[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) ->
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|
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) ->
|
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[10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) ->
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|
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) ->
|
|
[10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) ->
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|
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) ->
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[10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) ->
|
|
[15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) ->
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|
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) ->
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[10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) ->
|
|
[ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) ->
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|
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) ->
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|
[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) ->
|
|
[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) ->
|
|
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) ->
|
|
[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) ->
|
|
[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) ->
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[10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) ->
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[ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) ->
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[10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) ->
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[ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) ->
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[15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [67500 ps] PRE @ (0) ->
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[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) -> [15000 ps] RD @ (4, 624) -> [ 5000 ps] ACT @ (0, 492) ->
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[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) ->
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[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) ->
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[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) ->
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[10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) ->
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[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) ->
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[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) ->
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[10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) ->
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[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) ->
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[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) ->
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[10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) ->
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[15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) ->
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[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) ->
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[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) ->
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[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) ->
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[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) ->
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[10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) ->
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[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) ->
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[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) ->
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[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) ->
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[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) ->
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[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) ->
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[10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) ->
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[ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) ->
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[10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) ->
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[15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) ->
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[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) ->
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[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) ->
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[15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) ->
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[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) ->
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[10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) ->
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[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) ->
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[15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) ->
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[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) ->
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[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) ->
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[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) ->
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[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) ->
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[15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) ->
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[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) ->
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[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) ->
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[15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) ->
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[15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) ->
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[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) ->
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[10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) ->
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[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> [10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) ->
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[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) ->
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[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) ->
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[ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) ->
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[10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) ->
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[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) ->
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[10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) ->
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[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) ->
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[10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) ->
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[ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) ->
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[10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) ->
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[15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) ->
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[15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) ->
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[10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) ->
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[15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) ->
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[15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) ->
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[10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) ->
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[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) ->
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[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3627) ->
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[10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) ->
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[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) ->
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[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) ->
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[10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) ->
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[15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) ->
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[15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9219) ->
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[10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) ->
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[15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) ->
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[15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) ->
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[10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 304) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 296) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> [10000 ps] RD @ (0, 296) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 288) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 280) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [15000 ps] RD @ (0, 280) ->
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[10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> [10000 ps] RD @ (0, 280) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> [ 5000 ps] RD @ (0, 280) ->
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[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 272) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> [ 5000 ps] RD @ (0, 272) ->
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[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 264) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> [ 5000 ps] RD @ (0, 264) ->
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[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> [10000 ps] RD @ (0, 264) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> [ 5000 ps] RD @ (0, 264) ->
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[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 256) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> [ 5000 ps] RD @ (0, 256) ->
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[10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 248) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> [ 5000 ps] RD @ (0, 248) ->
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[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) ->
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[15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [15000 ps] RD @ (0, 248) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) ->
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[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> [10000 ps] ACT @ (0, 6274) ->
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[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [15000 ps] RD @ (0, 240) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [15000 ps] RD @ (0, 240) ->
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[10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> [10000 ps] ACT @ (0, 878) ->
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[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [15000 ps] RD @ (0, 232) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) ->
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[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> [10000 ps] ACT @ (0, 11866) ->
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[ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [15000 ps] RD @ (0, 232) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [15000 ps] RD @ (0, 232) ->
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[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> [10000 ps] ACT @ (0, 6470) ->
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[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [15000 ps] RD @ (0, 224) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) ->
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[10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> [10000 ps] ACT @ (0, 1074) ->
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[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [15000 ps] RD @ (0, 216) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [15000 ps] RD @ (0, 216) ->
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[10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> [10000 ps] ACT @ (0, 12062) ->
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[ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) ->
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[10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) ->
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[15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) ->
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[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5587) ->
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[10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) ->
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[15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) ->
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[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 191) ->
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[10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) ->
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[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) ->
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[15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11179) ->
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[10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) ->
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[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) ->
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[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5783) ->
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[10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) ->
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[15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) ->
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[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 387) ->
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[10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) ->
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[15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) ->
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[15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) ->
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[10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (4, 184) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) ->
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[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) ->
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[ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) ->
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[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) ->
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[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) ->
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[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) ->
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[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) ->
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[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) ->
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[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) ->
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[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) ->
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[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) ->
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[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) ->
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[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) ->
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[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) ->
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[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) ->
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[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) ->
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[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) ->
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[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) ->
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[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) ->
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[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) ->
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[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) ->
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[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) ->
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[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) ->
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[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) ->
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[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) ->
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[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) ->
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[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) ->
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[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) ->
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[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) ->
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[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) ->
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[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) ->
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[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) ->
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[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) ->
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[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) ->
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[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) ->
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[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) ->
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[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) ->
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[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) ->
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[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) ->
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[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) ->
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[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) ->
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[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) ->
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[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) ->
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[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) ->
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[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) ->
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[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) ->
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[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) ->
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[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) ->
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[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) ->
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[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) ->
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[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) ->
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[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) ->
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[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) ->
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[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) ->
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[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) ->
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[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) ->
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[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) ->
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[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) ->
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[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) ->
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[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) ->
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[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) ->
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[10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) ->
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[10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7447) ->
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[10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) ->
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[10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) ->
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[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 3130) -> [10000 ps] ACT @ (3, 3130) ->
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[15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) ->
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[15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) ->
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[ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> [ 5000 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) ->
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[10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) ->
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[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) ->
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[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) ->
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[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) ->
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[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) ->
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[10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) ->
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[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) ->
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[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) ->
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[10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) ->
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[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) ->
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[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) ->
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[10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) ->
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[15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) ->
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[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) ->
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[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) ->
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[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) ->
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[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) ->
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[10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) ->
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[ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) ->
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[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) ->
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[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) ->
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[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) ->
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[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) ->
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[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) ->
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[10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) ->
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[ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) ->
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[10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) ->
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[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) ->
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[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) ->
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[10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) ->
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[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) ->
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[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) ->
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[10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) ->
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[15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) ->
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[15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) ->
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[10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) ->
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[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) ->
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[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) ->
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[10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) ->
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[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) ->
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[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) ->
|
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[10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) ->
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[15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) ->
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[15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) ->
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[10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
|
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[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) ->
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[17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
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[ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) ->
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[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) ->
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[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) ->
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[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) ->
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[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) ->
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[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) ->
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[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) ->
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[10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) ->
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[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) ->
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|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) ->
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|
[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) ->
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[17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) ->
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|
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) ->
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|
[10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) ->
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|
[17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) ->
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[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) ->
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|
[10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) ->
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|
[17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) ->
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|
[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) ->
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[ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) ->
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|
--------------------------------
|
|
DONE TEST 2: RANDOM
|
|
Number of Operations: 2304
|
|
Time Started: 140100 ns
|
|
Time Done: 249710 ns
|
|
Average Rate: 47 ns/request
|
|
--------------------------------
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|
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|
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[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) ->
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|
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) ->
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|
[10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 249840000.0 ps
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|
|
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|
------- SUMMARY -------
|
|
Number of Writes = 4608
|
|
Number of Reads = 4608
|
|
Number of Success = 4604
|
|
Number of Fails = 4
|
|
Number of Injected Errors = 4
|
|
|
|
$stop called at time : 250810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
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|
run: Time (s): cpu = 00:00:16 ; elapsed = 00:47:46 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1332 ; free virtual = 24744
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## quit
|
|
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2805770 ms
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INFO: [Common 17-206] Exiting xsim at Wed Jul 5 14:58:39 2023...
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